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arm64: dts: qcom: Fix 'interrupt-map' parent address cells
authorRob Herring <robh@kernel.org>
Tue, 28 Sep 2021 19:22:09 +0000 (14:22 -0500)
committerBjorn Andersson <bjorn.andersson@linaro.org>
Sun, 24 Oct 2021 18:04:03 +0000 (13:04 -0500)
The 'interrupt-map' in several QCom SoCs is malformed. The '#address-cells'
size of the parent interrupt controller (the GIC) is not accounted for.

Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: linux-arm-msm@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210928192210.1842377-1-robh@kernel.org
arch/arm64/boot/dts/qcom/msm8998.dtsi
arch/arm64/boot/dts/qcom/sdm845.dtsi

index 1ecaa0d..63a3123 100644 (file)
                        interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "msi";
                        interrupt-map-mask = <0 0 0 0x7>;
-                       interrupt-map = <0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>,
-                                       <0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>,
-                                       <0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>,
-                                       <0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-map = <0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>;
 
                        clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
                                 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
index bfb3fb7..a4e5612 100644 (file)
                        interrupt-names = "msi";
                        #interrupt-cells = <1>;
                        interrupt-map-mask = <0 0 0 0x7>;
-                       interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
-                                       <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
-                                       <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
-                                       <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+                       interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+                                       <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+                                       <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+                                       <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 
                        clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
                                 <&gcc GCC_PCIE_0_AUX_CLK>,
                        interrupt-names = "msi";
                        #interrupt-cells = <1>;
                        interrupt-map-mask = <0 0 0 0x7>;
-                       interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
-                                       <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
-                                       <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
-                                       <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+                       interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+                                       <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+                                       <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+                                       <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 
                        clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
                                 <&gcc GCC_PCIE_1_AUX_CLK>,