ASoC: sun8i-codec: Fix AIF1_MXR_SRC field names

Even though they are for the left channel mixer, they are documented as
"MXR_SRC". This matches the naming scheme used for the main DAC. The "R"
is part of the abbreviation for "mixer", not a reference to the channel.

Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20200831034852.18841-5-samuel@sholland.org
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
index 68c8eda..def3a00 100644 (file)
--- a/sound/soc/sunxi/sun8i-codec.c
+++ b/sound/soc/sunxi/sun8i-codec.c
@@ -55,10 +55,10 @@
 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA           15
 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA           14
 #define SUN8I_AIF1_MXR_SRC                             0x04c
-#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF1DA0L       15
-#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACL       14
-#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_ADCL           13
-#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACR       12
+#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L       15
+#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL       14
+#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_ADCL           13
+#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACR       12
 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R       11
 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR       10
 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR           9
@@ -374,18 +374,18 @@ static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = {
 static const struct snd_kcontrol_new sun8i_input_mixer_controls[] = {
        SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital ADC Capture Switch",
                        SUN8I_AIF1_MXR_SRC,
-                       SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF1DA0L,
+                       SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L,
                        SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R, 1, 0),
        SOC_DAPM_DOUBLE("AIF2 Digital ADC Capture Switch", SUN8I_AIF1_MXR_SRC,
-                       SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACL,
+                       SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL,
                        SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR, 1, 0),
        SOC_DAPM_DOUBLE("AIF1 Data Digital ADC Capture Switch",
                        SUN8I_AIF1_MXR_SRC,
-                       SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_ADCL,
+                       SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_ADCL,
                        SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR, 1, 0),
        SOC_DAPM_DOUBLE("AIF2 Inv Digital ADC Capture Switch",
                        SUN8I_AIF1_MXR_SRC,
-                       SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACR,
+                       SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACR,
                        SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL, 1, 0),
 };