qemu_irq irq;
} PIIX4PMState;
+#define RSM_STS (1 << 15)
+#define PWRBTN_STS (1 << 8)
#define RTC_EN (1 << 10)
#define PWRBTN_EN (1 << 8)
#define GBL_EN (1 << 5)
case 0: /* soft power off */
qemu_system_shutdown_request();
break;
+ case 1:
+ /* RSM_STS should be set on resume. Pretend that resume
+ was caused by power button */
+ s->pmsts |= (RSM_STS | PWRBTN_STS);
+ qemu_system_reset_request();
+#if defined(TARGET_I386)
+ cmos_set_s3_resume();
+#endif
default:
break;
}
return 0;
}
+static void piix4_reset(void *opaque)
+{
+ PIIX4PMState *s = opaque;
+ uint8_t *pci_conf = s->dev.config;
+
+ pci_conf[0x58] = 0;
+ pci_conf[0x59] = 0;
+ pci_conf[0x5a] = 0;
+ pci_conf[0x5b] = 0;
+}
+
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
qemu_irq sci_irq)
{
s->smbus = i2c_init_bus();
s->irq = sci_irq;
+ qemu_register_reset(piix4_reset, s);
+
return s->smbus;
}
initrd_filename, 0, cpu_model);
}
+/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
+ BIOS will read it and start S3 resume at POST Entry */
+void cmos_set_s3_resume(void)
+{
+ if (rtc_state)
+ rtc_set_memory(rtc_state, 0xF, 0xFE);
+}
+
QEMUMachine pc_machine = {
.name = "pc",
.desc = "Standard PC",
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
void rtc_set_memory(RTCState *s, int addr, int val);
void rtc_set_date(RTCState *s, const struct tm *tm);
+void cmos_set_s3_resume(void);
/* pc.c */
extern int fd_bootchk;