Add an assertion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34596 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp
index 0938e3a..9135edc 100644 (file)
--- a/lib/CodeGen/RegisterScavenging.cpp
+++ b/lib/CodeGen/RegisterScavenging.cpp
@@ -76,10 +76,12 @@ void RegScavenger::forward() {
     const MachineOperand &MO = MI->getOperand(i);
     if (!MO.isReg() || !MO.isDef())
       continue;
+    unsigned Reg = MO.getReg();
     // Skip two-address destination operand.
-    if (TID->findTiedToSrcOperand(i) != -1)
+    if (TID->findTiedToSrcOperand(i) != -1) {
+      assert(isUsed(Reg));
       continue;
-    unsigned Reg = MO.getReg();
+    }
     assert(isUnused(Reg) || isReserved(Reg));
     if (!MO.isDead())
       setUsed(Reg);