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clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for spdif_8ch
author
zhangqing
<zhangqing@rock-chips.com>
Mon, 25 Jan 2016 16:56:01 +0000
(08:56 -0800)
committer
Heiko Stuebner
<heiko@sntech.de>
Mon, 25 Jan 2016 10:04:51 +0000
(11:04 +0100)
SPDIF_8CH set freq need to select parent and calculate parent freq.
so just mark it as the CLK_SET_RATE_PARENT flag.
Signed-off-by: zhangqing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-rk3368.c
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diff --git
a/drivers/clk/rockchip/clk-rk3368.c
b/drivers/clk/rockchip/clk-rk3368.c
index
dab759b
..
caf0b94
100644
(file)
--- a/
drivers/clk/rockchip/clk-rk3368.c
+++ b/
drivers/clk/rockchip/clk-rk3368.c
@@
-353,7
+353,7
@@
static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
COMPOSITE_FRAC(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(32), 0,
RK3368_CLKGATE_CON(6), 5, GFLAGS),
- COMPOSITE_NODIV(SCLK_SPDIF_8CH, "sclk_spdif_8ch", mux_spdif_8ch_p,
0
,
+ COMPOSITE_NODIV(SCLK_SPDIF_8CH, "sclk_spdif_8ch", mux_spdif_8ch_p,
CLK_SET_RATE_PARENT
,
RK3368_CLKSEL_CON(31), 8, 2, MFLAGS,
RK3368_CLKGATE_CON(6), 6, GFLAGS),
COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,