timing adjustment...

diff --git a/de1_nes/de1_nes.qsf b/de1_nes/de1_nes.qsf
index 59bc0c7..4d27b1f 100644 (file)
--- a/de1_nes/de1_nes.qsf
+++ b/de1_nes/de1_nes.qsf
@@ -112,4 +112,33 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"\r
 set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation\r
 set_global_assignment -name SDC_FILE "mos6502-timing.sdc"\r
+\r
+\r
+#timing opimizations....\r
+#set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"\r
+#set_global_assignment -name SMART_RECOMPILE ON\r
+#set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"\r
+#set_global_assignment -name ENABLE_DRC_SETTINGS ON\r
+#set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED\r
+#set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON\r
+#set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON\r
+#set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON\r
+#set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM\r
+#set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL\r
+#set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON\r
+#set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON\r
+#set_global_assignment -name FITTER_EFFORT "STANDARD FIT"\r
+#set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION ALWAYS\r
+#set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON\r
+#set_global_assignment -name MUX_RESTRUCTURE OFF\r
+#set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON\r
+#set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON\r
+#set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON\r
+#set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ALWAYS\r
+#set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON\r
+#set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON\r
+#set_global_assignment -name AUTO_RAM_RECOGNITION ON\r
+#set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION ALWAYS\r
+#set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"\r
+#set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to base_clk\r
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file

diff --git a/de1_nes/mos6502-timing.sdc b/de1_nes/mos6502-timing.sdc
index 31cf764..87fa99a 100644 (file)
--- a/de1_nes/mos6502-timing.sdc
+++ b/de1_nes/mos6502-timing.sdc
@@ -1,2 +1,3 @@
 create_clock -name base_clock -period 20 [get_ports {base_clk}]\r
-create_generated_clock -name cpu_clock -source [get_ports {base_clk}] -divide_by 2 
\ No newline at end of file
+#create_generated_clock -name cpu_clock -source [get_ports {base_clk}] -divide_by 24 -invert [get_registers {clock_divider:clock_inst|cpu_clk_wk}]\r
+#create_generated_clock -name emu_ppu_clock -source [get_ports {base_clk}] -divide_by 4 -invert [get_registers {clock_divider:clock_inst|counter_register:cpu_clk_cnt|d_flip_flop:counter_reg_inst|q[1]}]\r

diff --git a/doc/mos6502-clock.xlsx b/doc/mos6502-clock.xlsx
index a075f42..8454f4c 100644 (file)
Binary files a/doc/mos6502-clock.xlsx and b/doc/mos6502-clock.xlsx differ