#define MPC8544_I2C_IRQ 43
#define RTC_REGS_OFFSET 0x68
+#define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000)
+
struct boot_info
{
uint32_t dt_base;
int fdt_size;
void *fdt;
uint8_t hypercall[16];
- uint32_t clock_freq = 400000000;
- uint32_t tb_freq = 400000000;
+ uint32_t clock_freq = PLATFORM_CLK_FREQ_HZ;
+ uint32_t tb_freq = PLATFORM_CLK_FREQ_HZ;
int i;
char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";
char *soc;
env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i;
env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0;
- ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500);
+ ppc_booke_timers_init(cpu, PLATFORM_CLK_FREQ_HZ, PPC_TIMER_E500);
/* Register reset handler */
if (!i) {