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drm/i915/dp: Fix inconsistent indenting
authorChris Wilson <chris@chris-wilson.co.uk>
Tue, 20 Nov 2018 20:24:39 +0000 (20:24 +0000)
committerChris Wilson <chris@chris-wilson.co.uk>
Tue, 4 Dec 2018 09:32:57 +0000 (09:32 +0000)
Always show the FEC capability as it is initialised to 0 before error.
Fixing,

drivers/gpu/drm/i915/intel_dp.c:3846 intel_dp_get_dsc_sink_cap() warn: inconsistent indenting

Fixes: 08cadae8e157 ("i915/dp/fec: Cache the FEC_CAPABLE DPCD register")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181120202439.13017-2-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/intel_dp.c

index a6907a1..fdd2cbc 100644 (file)
@@ -4026,15 +4026,14 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
                DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
                              (int)sizeof(intel_dp->dsc_dpcd),
                              intel_dp->dsc_dpcd);
+
                /* FEC is supported only on DP 1.4 */
-               if (!intel_dp_is_edp(intel_dp)) {
-                       if (drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
-                                             &intel_dp->fec_capable) < 0)
-                               DRM_ERROR("Failed to read FEC DPCD register\n");
+               if (!intel_dp_is_edp(intel_dp) &&
+                   drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
+                                     &intel_dp->fec_capable) < 0)
+                       DRM_ERROR("Failed to read FEC DPCD register\n");
 
-               DRM_DEBUG_KMS("FEC CAPABILITY: %x\n",
-                             intel_dp->fec_capable);
-               }
+               DRM_DEBUG_KMS("FEC CAPABILITY: %x\n", intel_dp->fec_capable);
        }
 }