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drm/vc4: crtc: Clear the PixelValve FIFO on disable
author
Maxime Ripard
<maxime@cerno.tech>
Thu, 3 Sep 2020 08:01:02 +0000
(10:01 +0200)
committer
Maxime Ripard
<maxime@cerno.tech>
Mon, 7 Sep 2020 16:04:12 +0000
(18:04 +0200)
In order to avoid a stale pixel getting stuck on mode change or a disable
/ enable cycle, we need to make sure to flush the PV FIFO on disable.
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Link:
https://patchwork.freedesktop.org/patch/msgid/26fe48b09d77088679ed0c8cb8cf0db2f108195e.1599120059.git-series.maxime@cerno.tech
drivers/gpu/drm/vc4/vc4_crtc.c
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diff --git
a/drivers/gpu/drm/vc4/vc4_crtc.c
b/drivers/gpu/drm/vc4/vc4_crtc.c
index
4c23cf8
..
73d9187
100644
(file)
--- a/
drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/
drivers/gpu/drm/vc4/vc4_crtc.c
@@
-424,8
+424,7
@@
static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
if (vc4_encoder->post_crtc_disable)
vc4_encoder->post_crtc_disable(encoder);
- CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN);
-
+ vc4_crtc_pixelvalve_reset(crtc);
vc4_hvs_atomic_disable(crtc, old_state);
if (vc4_encoder->post_crtc_powerdown)