drm/amdgpu: only set cp active field for kiq queue

The mec ucode will set the CP_HQD_ACTIVE bit while the queue is mapped by
MAP_QUEUES packet. So we only need set cp active field for kiq queue.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 468f1b1..874f641 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3337,8 +3337,11 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
        tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
        mqd->cp_hqd_ib_control = tmp;
 
-       /* activate the queue */
-       mqd->cp_hqd_active = 1;
+       /* map_queues packet doesn't need activate the queue,
+        * so only kiq need set this field.
+        */
+       if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
+               mqd->cp_hqd_active = 1;
 
        return 0;
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index cfc1403..46f0533 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4558,8 +4558,11 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
        mqd->cp_hqd_eop_wptr_mem = RREG32(mmCP_HQD_EOP_WPTR_MEM);
        mqd->cp_hqd_eop_dones = RREG32(mmCP_HQD_EOP_DONES);
 
-       /* activate the queue */
-       mqd->cp_hqd_active = 1;
+       /* map_queues packet doesn't need activate the queue,
+        * so only kiq need set this field.
+        */
+       if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
+               mqd->cp_hqd_active = 1;
 
        return 0;
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 388a38f..46ab467 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3370,8 +3370,11 @@ static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
        tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
        mqd->cp_hqd_ib_control = tmp;
 
-       /* activate the queue */
-       mqd->cp_hqd_active = 1;
+       /* map_queues packet doesn't need activate the queue,
+        * so only kiq need set this field.
+        */
+       if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
+               mqd->cp_hqd_active = 1;
 
        return 0;
 }