add pattern to load constant 0 into a predicate reg

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24164 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/IA64/IA64InstrInfo.td b/lib/Target/IA64/IA64InstrInfo.td
index 7620f4a..26d5e2c 100644 (file)
--- a/lib/Target/IA64/IA64InstrInfo.td
+++ b/lib/Target/IA64/IA64InstrInfo.td
@@ -361,6 +361,8 @@ def SELECTINT : Pat<(select PR:$which, GR:$src1, GR:$src2),
 def : Pat<(i64 immSExt14:$imm), (ADDS r0, immSExt14:$imm)>;
 def : Pat<(i64 imm64:$imm), (MOVL imm64:$imm)>;
 def : Pat<(i1 -1), (CMPEQ r0, r0)>; // TODO: this should just be a ref to p0
+def : Pat<(i1  0), (CMPNE r0, r0)>; // TODO: any instruction actually *using*
+                                    //       this predicate should be killed!
 
 // TODO: support postincrement (reg, imm9) loads+stores - this needs more
 // tablegen support