}
return cpu->env.v7m.scr[attrs.secure];
case 0xd14: /* Configuration Control. */
- /* The BFHFNMIGN bit is the only non-banked bit; we
- * keep it in the non-secure copy of the register.
+ /*
+ * Non-banked bits: BFHFNMIGN (stored in the NS copy of the register)
+ * and TRD (stored in the S copy of the register)
*/
val = cpu->env.v7m.ccr[attrs.secure];
val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;
cpu->env.v7m.scr[attrs.secure] = value;
break;
case 0xd14: /* Configuration Control. */
+ {
+ uint32_t mask;
+
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
/* Enforce RAZ/WI on reserved and must-RAZ/WI bits */
- value &= (R_V7M_CCR_STKALIGN_MASK |
- R_V7M_CCR_BFHFNMIGN_MASK |
- R_V7M_CCR_DIV_0_TRP_MASK |
- R_V7M_CCR_UNALIGN_TRP_MASK |
- R_V7M_CCR_USERSETMPEND_MASK |
- R_V7M_CCR_NONBASETHRDENA_MASK);
+ mask = R_V7M_CCR_STKALIGN_MASK |
+ R_V7M_CCR_BFHFNMIGN_MASK |
+ R_V7M_CCR_DIV_0_TRP_MASK |
+ R_V7M_CCR_UNALIGN_TRP_MASK |
+ R_V7M_CCR_USERSETMPEND_MASK |
+ R_V7M_CCR_NONBASETHRDENA_MASK;
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8_1M) && attrs.secure) {
+ /* TRD is always RAZ/WI from NS */
+ mask |= R_V7M_CCR_TRD_MASK;
+ }
+ value &= mask;
if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
/* v8M makes NONBASETHRDENA and STKALIGN be RES1 */
cpu->env.v7m.ccr[attrs.secure] = value;
break;
+ }
case 0xd24: /* System Handler Control and State (SHCSR) */
if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) {
goto bad_offset;
FIELD(V7M_CCR, DC, 16, 1)
FIELD(V7M_CCR, IC, 17, 1)
FIELD(V7M_CCR, BP, 18, 1)
+FIELD(V7M_CCR, LOB, 19, 1)
+FIELD(V7M_CCR, TRD, 20, 1)
/* V7M SCR bits */
FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)