drm/vc4: hdmi: Fix timings for interlaced modes

Increase the number of post-sync blanking lines on odd fields instead of
decreasing it on even fields. This makes the total number of lines
properly match the modelines.

Additionally fix the value of PV_VCONTROL_ODD_DELAY, which did not take
pixels_per_clock into account, causing some displays to invert the
fields when driven by bcm2711.

Fixes: 682e62c45406 ("drm/vc4: Fix support for interlaced modes on HDMI.")
Signed-off-by: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com>
Link: https://lore.kernel.org/r/20220613144800.326124-31-maxime@cerno.tech
Signed-off-by: Maxime Ripard <maxime@cerno.tech>

diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index e144ff1..5efa2d5 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -347,7 +347,8 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encode
                                 PV_HORZB_HACTIVE));
 
        CRTC_WRITE(PV_VERTA,
-                  VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
+                  VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
+                                interlace,
                                 PV_VERTA_VBP) |
                   VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
                                 PV_VERTA_VSYNC));
@@ -359,7 +360,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encode
        if (interlace) {
                CRTC_WRITE(PV_VERTA_EVEN,
                           VC4_SET_FIELD(mode->crtc_vtotal -
-                                        mode->crtc_vsync_end - 1,
+                                        mode->crtc_vsync_end,
                                         PV_VERTA_VBP) |
                           VC4_SET_FIELD(mode->crtc_vsync_end -
                                         mode->crtc_vsync_start,
@@ -379,7 +380,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encode
                           PV_VCONTROL_CONTINUOUS |
                           (is_dsi ? PV_VCONTROL_DSI : 0) |
                           PV_VCONTROL_INTERLACE |
-                          VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
+                          VC4_SET_FIELD(mode->htotal * pixel_rep / (2 * ppc),
                                         PV_VCONTROL_ODD_DELAY));
                CRTC_WRITE(PV_VSYNCD_EVEN, 0);
        } else {

diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 3e97d97..6f71310 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -984,12 +984,12 @@ static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
                                   VC4_HDMI_VERTA_VFP) |
                     VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
        u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
-                    VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
+                    VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
+                                  interlaced,
                                   VC4_HDMI_VERTB_VBP));
        u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
                          VC4_SET_FIELD(mode->crtc_vtotal -
-                                       mode->crtc_vsync_end -
-                                       interlaced,
+                                       mode->crtc_vsync_end,
                                        VC4_HDMI_VERTB_VBP));
        unsigned long flags;
 
@@ -1037,12 +1037,12 @@ static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
                                   VC5_HDMI_VERTA_VFP) |
                     VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
        u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
-                    VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
+                    VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
+                                  interlaced,
                                   VC4_HDMI_VERTB_VBP));
        u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
                          VC4_SET_FIELD(mode->crtc_vtotal -
-                                       mode->crtc_vsync_end -
-                                       interlaced,
+                                       mode->crtc_vsync_end,
                                        VC4_HDMI_VERTB_VBP));
        unsigned long flags;
        unsigned char gcp;