2003-10-16 H.J. Lu <hongjiu.lu@intel.com>

	* gas/alpha/elf-reloc-8.d: Updated.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 1fde74d..653502f 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2003-10-16  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * gas/alpha/elf-reloc-8.d: Updated.
+
 2003-10-10  Dave Brolley  <brolley@redhat.com>
 
        * gas/frv/allinsn.s: Use preoperly aligned registers.

diff --git a/gas/testsuite/gas/alpha/elf-reloc-8.d b/gas/testsuite/gas/alpha/elf-reloc-8.d
index 8ba78c3..32ebf97 100644 (file)
--- a/gas/testsuite/gas/alpha/elf-reloc-8.d
+++ b/gas/testsuite/gas/alpha/elf-reloc-8.d
@@ -311,20 +311,20 @@ OFFSET *TYPE *VALUE
 
 RELOCATION RECORDS FOR \[\.eh_frame\]:
 OFFSET *TYPE *VALUE 
-0*000001c SREL32            \.init\.text
-0*0000034 SREL32            \.init\.text\+0x0*0000050
-0*0000048 SREL32            \.init\.text\+0x0*0000080
-0*000005c SREL32            \.init\.text\+0x0*00000b0
-0*0000080 SREL32            \.init\.text\+0x0*00002c0
-0*00000a0 SREL32            \.init\.text\+0x0*00005a0
-0*00000b8 SREL32            \.init\.text\+0x0*00005f0
-0*00000cc SREL32            \.init\.text\+0x0*0000610
-0*00000e0 SREL32            \.init\.text\+0x0*0000630
-0*00000fc SREL32            \.init\.text\+0x0*0000750
-0*0000120 SREL32            \.init\.text\+0x0*0000990
-0*000013c SREL32            \.init\.text\+0x0*0000a10
-0*0000150 SREL32            \.init\.text\+0x0*0000a20
-0*0000164 SREL32            \.init\.text\+0x0*0000a40
-0*000017c SREL32            \.init\.text\+0x0*0000a90
-0*0000190 SREL32            \.init\.text\+0x0*0000aa0
-0*00001a4 SREL32            \.text
+0*000001b SREL32            \.init\.text
+0*0000031 SREL32            \.init\.text\+0x0*0000050
+0*0000042 SREL32            \.init\.text\+0x0*0000080
+0*0000053 SREL32            \.init\.text\+0x0*00000b0
+0*0000074 SREL32            \.init\.text\+0x0*00002c0
+0*0000092 SREL32            \.init\.text\+0x0*00005a0
+0*00000aa SREL32            \.init\.text\+0x0*00005f0
+0*00000bb SREL32            \.init\.text\+0x0*0000610
+0*00000cc SREL32            \.init\.text\+0x0*0000630
+0*00000e6 SREL32            \.init\.text\+0x0*0000750
+0*000010a SREL32            \.init\.text\+0x0*0000990
+0*0000124 SREL32            \.init\.text\+0x0*0000a10
+0*0000135 SREL32            \.init\.text\+0x0*0000a20
+0*0000146 SREL32            \.init\.text\+0x0*0000a40
+0*000015e SREL32            \.init\.text\+0x0*0000a90
+0*000016f SREL32            \.init\.text\+0x0*0000aa0
+0*0000180 SREL32            \.text