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clk: xgene: Add missing parenthesis when clearing divider value
authorLoc Ho <lho@apm.com>
Mon, 29 Feb 2016 21:15:43 +0000 (14:15 -0700)
committerStephen Boyd <sboyd@codeaurora.org>
Thu, 3 Mar 2016 19:37:15 +0000 (11:37 -0800)
In the initial fix for non-zero divider shift value, the parenthesis
was missing after the negate operation. This patch adds the required
parenthesis. Otherwise, lower bits may be cleared unintentionally.

Signed-off-by: Loc Ho <lho@apm.com>
Acked-by: Toan Le <toanle@apm.com>
Fixes: 1382ea631ddd ("clk: xgene: Fix divider with non-zero shift value")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/clk-xgene.c

index bd7156b..d73450b 100644 (file)
@@ -376,8 +376,8 @@ static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate,
                /* Set new divider */
                data = xgene_clk_read(pclk->param.divider_reg +
                                pclk->param.reg_divider_offset);
-               data &= ~((1 << pclk->param.reg_divider_width) - 1)
-                               << pclk->param.reg_divider_shift;
+               data &= ~(((1 << pclk->param.reg_divider_width) - 1)
+                               << pclk->param.reg_divider_shift);
                data |= divider;
                xgene_clk_write(data, pclk->param.divider_reg +
                                        pclk->param.reg_divider_offset);