let HighLatency = 25;
let MispredictPenalty = 14; // Minimum branch misdirection penalty
let PostRAScheduler = 1;
-
- // FIXME: SSE4/AVX is unimplemented. This flag is set to allow
- // the scheduler to assign a default model to unrecognized opcodes.
- let CompleteModel = 0;
}
let SchedModel = BtVer2Model in {
def : WriteRes<WriteStore, [JSAGU]>;
def : WriteRes<WriteMove, [JALU01]>;
+// Treat misc copies as a move.
+def : InstRW<[WriteMove], (instrs COPY)>;
+
////////////////////////////////////////////////////////////////////////////////
// Idioms that clear a register, like xorps %xmm0, %xmm0.
// These can often bypass execution ports completely.