apu work started..

diff --git a/de0_cv_nes/apu.vhd b/de0_cv_nes/apu.vhd
new file mode 100644 (file)
index 0000000..fd8b33a
--- /dev/null
+++ b/de0_cv_nes/apu.vhd
@@ -0,0 +1,143 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity apu is 
+    port (
+        pi_rst_n       : in std_logic;
+        pi_base_clk    : in std_logic;
+        pi_cpu_en      : in std_logic_vector (7 downto 0);
+        pi_rnd_en      : in std_logic_vector (3 downto 0);
+        pi_ce_n        : in std_logic;
+
+        --cpu i/f
+        pio_oe_n       : inout std_logic;
+        pio_we_n       : inout std_logic;
+        pio_cpu_addr   : inout std_logic_vector (15 downto 0);
+        pio_cpu_d      : inout std_logic_vector (7 downto 0);
+        po_rdy         : out std_logic;
+
+        --sprite i/f
+        po_spr_ce_n    : out std_logic;
+        po_spr_rd_n    : out std_logic;
+        po_spr_wr_n    : out std_logic;
+        po_spr_addr    : out std_logic_vector (7 downto 0);
+        po_spr_data    : out std_logic_vector (7 downto 0)
+    );
+end apu;
+
+architecture rtl of apu is
+
+
+constant OAM_DMA   : std_logic_vector(4 downto 0) := "10100";
+constant OAM_JP1   : std_logic_vector(4 downto 0) := "10110";
+constant OAM_JP2   : std_logic_vector(4 downto 0) := "10111";
+
+--oamaddr=0x2003
+constant OAMADDR   : std_logic_vector(15 downto 0) := "0010000000000011";
+--oamdata=0x2004
+constant OAMDATA   : std_logic_vector(15 downto 0) := "0010000000000100";
+
+type dma_state is (
+    idle,
+    reg_set,
+    dma_init,
+    rd_data,
+    wr_data,
+    dma_end
+);
+
+signal reg_dma_cur_state      : dma_state;
+signal reg_dma_next_state     : dma_state;
+
+
+signal reg_cpu_oe_n     : std_logic;
+signal reg_cpu_we_n     : std_logic;
+signal reg_cpu_addr     : std_logic_vector (15 downto 0);
+signal reg_cpu_d        : std_logic_vector (7 downto 0);
+signal reg_rdy          : std_logic;
+
+        --sprite i/f
+signal reg_spr_ce_n     : std_logic;
+signal reg_spr_rd_n     : std_logic;
+signal reg_spr_wr_n     : std_logic;
+signal reg_spr_addr     : std_logic_vector (7 downto 0);
+signal reg_spr_data     : std_logic_vector (7 downto 0);
+
+begin
+
+    --state machine (state transition)...
+    dma_stat_tx_p : process (pi_rst_n, pi_base_clk)
+    begin
+        if (pi_rst_n = '0') then
+            reg_dma_cur_state <= idle;
+        elsif (rising_edge(pi_base_clk)) then
+            reg_dma_cur_state <= reg_dma_next_state;
+        end if;--if (pi_rst_n = '0') then
+    end process;
+
+    --state change to next.
+    dma_stat_p : process (reg_dma_cur_state)
+    begin
+        case reg_dma_cur_state is
+            when idle =>
+                reg_dma_next_state <= reg_dma_cur_state;
+            when reg_set =>
+                reg_dma_next_state <= reg_dma_cur_state;
+            when dma_init =>
+                reg_dma_next_state <= reg_dma_cur_state;
+            when rd_data =>
+                reg_dma_next_state <= reg_dma_cur_state;
+            when wr_data =>
+                reg_dma_next_state <= reg_dma_cur_state;
+            when dma_end =>
+                reg_dma_next_state <= reg_dma_cur_state;
+        end case;
+    end process;
+
+    pio_oe_n       <= reg_cpu_oe_n;
+    pio_we_n       <= reg_cpu_we_n;
+    pio_cpu_addr   <= reg_cpu_addr;
+    pio_cpu_d      <= reg_cpu_d;
+    po_rdy         <= reg_rdy;
+
+    po_spr_ce_n    <= reg_spr_ce_n;
+    po_spr_rd_n    <= reg_spr_rd_n;
+    po_spr_wr_n    <= reg_spr_wr_n;
+    po_spr_addr    <= reg_spr_addr;
+    po_spr_data    <= reg_spr_data;
+
+    cpu_out_p : process (pi_rst_n, pi_base_clk)
+    begin
+        if (pi_rst_n = '0') then
+            reg_cpu_oe_n <= 'Z';
+            reg_cpu_we_n <= 'Z';
+            reg_cpu_addr <= (others => 'Z');
+            reg_cpu_d    <= (others => 'Z');
+            reg_rdy      <= '1';
+        elsif (rising_edge(pi_base_clk)) then
+            reg_cpu_oe_n <= 'Z';
+            reg_cpu_we_n <= 'Z';
+            reg_cpu_addr <= (others => 'Z');
+            reg_cpu_d    <= (others => 'Z');
+            reg_rdy      <= '1';
+        end if;--if (pi_rst_n = '0') then
+    end process;
+
+    spr_out_p : process (pi_rst_n, pi_base_clk)
+    begin
+        if (pi_rst_n = '0') then
+            reg_spr_ce_n <= 'Z';
+            reg_spr_rd_n <= 'Z';
+            reg_spr_wr_n <= 'Z';
+            reg_spr_addr <= (others => 'Z');
+            reg_spr_data <= (others => 'Z');
+        elsif (rising_edge(pi_base_clk)) then
+            reg_spr_ce_n <= 'Z';
+            reg_spr_rd_n <= 'Z';
+            reg_spr_wr_n <= 'Z';
+            reg_spr_addr <= (others => 'Z');
+            reg_spr_data <= (others => 'Z');
+        end if;--if (pi_rst_n = '0') then
+    end process;
+
+end rtl;

diff --git a/de0_cv_nes/de0_cv_nes.qsf b/de0_cv_nes/de0_cv_nes.qsf
index 87455f6..568ab93 100644 (file)
--- a/de0_cv_nes/de0_cv_nes.qsf
+++ b/de0_cv_nes/de0_cv_nes.qsf
@@ -97,12 +97,13 @@ set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to pi_base_clk
 #project files\r
 set_global_assignment -name VHDL_FILE mem/ram.vhd\r
 set_global_assignment -name VHDL_FILE chip_selector.vhd\r
+set_global_assignment -name VHDL_FILE apu.vhd\r
 \r
 #ppu\r
-set_global_assignment -name VHDL_FILE mem/chr_rom.vhd\r
-set_global_assignment -name VHDL_FILE ppu/render.vhd\r
-set_global_assignment -name VHDL_FILE ppu/ppu.vhd\r
-#set_global_assignment -name VHDL_FILE dummy-ppu.vhd\r
+#set_global_assignment -name VHDL_FILE mem/chr_rom.vhd\r
+#set_global_assignment -name VHDL_FILE ppu/render.vhd\r
+#set_global_assignment -name VHDL_FILE ppu/ppu.vhd\r
+set_global_assignment -name VHDL_FILE dummy-ppu.vhd\r
 \r
 #cpu\r
 set_global_assignment -name VHDL_FILE mem/prg_rom.vhd\r

diff --git a/de0_cv_nes/de0_cv_nes.vhd b/de0_cv_nes/de0_cv_nes.vhd
index fc179c1..433bbef 100644 (file)
--- a/de0_cv_nes/de0_cv_nes.vhd
+++ b/de0_cv_nes/de0_cv_nes.vhd
@@ -40,8 +40,8 @@ architecture rtl of de0_cv_nes is
                 pi_nmi_n       : in std_logic;\r
                 po_oe_n        : out std_logic;\r
                 po_we_n        : out std_logic;\r
-                po_addr        : out std_logic_vector ( 15 downto 0);\r
-                pio_d_io       : inout std_logic_vector ( 7 downto 0)\r
+                po_addr        : out std_logic_vector (15 downto 0);\r
+                pio_d_io       : inout std_logic_vector (7 downto 0)\r
         );
     end component;
 
@@ -201,6 +201,30 @@ architecture rtl of de0_cv_nes is
             );\r
     end component;\r
 \r
+    component apu\r
+        port (\r
+            pi_rst_n       : in std_logic;\r
+            pi_base_clk    : in std_logic;\r
+            pi_cpu_en      : in std_logic_vector (7 downto 0);\r
+            pi_rnd_en      : in std_logic_vector (3 downto 0);\r
+            pi_ce_n        : in std_logic;\r
+\r
+            --cpu i/f\r
+            pio_oe_n       : inout std_logic;\r
+            pio_we_n       : inout std_logic;\r
+            pio_cpu_addr   : inout std_logic_vector (15 downto 0);\r
+            pio_cpu_d      : inout std_logic_vector (7 downto 0);\r
+            po_rdy         : out std_logic;\r
+\r
+            --sprite i/f\r
+            po_spr_ce_n    : out std_logic;\r
+            po_spr_rd_n    : out std_logic;\r
+            po_spr_wr_n    : out std_logic;\r
+            po_spr_addr    : out std_logic_vector (7 downto 0);\r
+            po_spr_data    : out std_logic_vector (7 downto 0)\r
+        );\r
+    end component;\r
+\r
 constant ram_2k     : integer := 11;    --2k = 11   bit width.\r
 constant rom_32k    : integer := 15;    --32k = 15  bit width.\r
 constant vram_1k    : integer := 10;    --1k = 10   bit width.\r
@@ -453,7 +477,28 @@ begin
             po_b\r
             );\r
 \r
-    wr_rdy <= '1';\r
+    apu_inst : apu port map (\r
+            pi_rst_n, \r
+            pi_base_clk,\r
+            wr_cpu_en, \r
+            wr_rnd_en,\r
+            wr_apu_ce_n,\r
+\r
+            --cpu i/f\r
+            wr_oe_n,\r
+            wr_we_n,\r
+            wr_addr,\r
+            wr_d_io,\r
+            wr_rdy,\r
+\r
+            --sprite i/f\r
+            wr_spr_ce_n,\r
+            wr_spr_rd_n,\r
+            wr_spr_wr_n,\r
+            wr_spr_addr,\r
+            wr_spr_data\r
+        );\r
+\r
     wr_irq_n <= '1';\r
 \r
     po_dbg_cnt <= reg_dbg_cnt;\r

diff --git a/de0_cv_nes/dummy-ppu.vhd b/de0_cv_nes/dummy-ppu.vhd
index 410bd7b..73a4671 100644 (file)
--- a/de0_cv_nes/dummy-ppu.vhd
+++ b/de0_cv_nes/dummy-ppu.vhd
@@ -68,16 +68,16 @@ begin
     po_ppu_scroll_x    <= (others => 'Z');\r
     po_ppu_scroll_y    <= (others => 'Z');\r
 \r
-    --- initiate nmi.\r
-    nmi_p: process\r
-    constant nmi_wait     : time := 880us;\r
-    constant vblank_time     : time := 1000 us;\r
-    begin\r
-        po_vblank_n <= '1';\r
-        wait for nmi_wait;\r
-        po_vblank_n <= '0';\r
-        wait for vblank_time ;\r
-    end process;\r
+--    --- initiate nmi.\r
+--    nmi_p: process\r
+--    constant nmi_wait     : time := 880us;\r
+--    constant vblank_time     : time := 1000 us;\r
+--    begin\r
+--        po_vblank_n <= '1';\r
+--        wait for nmi_wait;\r
+--        po_vblank_n <= '0';\r
+--        wait for vblank_time ;\r
+--    end process;\r
 \r
 end rtl;\r
 \r

diff --git a/de0_cv_nes/mem/prg_rom.vhd b/de0_cv_nes/mem/prg_rom.vhd
index a37cea1..e7658eb 100644 (file)
--- a/de0_cv_nes/mem/prg_rom.vhd
+++ b/de0_cv_nes/mem/prg_rom.vhd
@@ -42,12 +42,12 @@ function rom_fill return rom_array is
 
 --for GHDL environment
 --itinialize with the rom_fill function.
---signal p_rom : rom_array := rom_fill;
+signal p_rom : rom_array := rom_fill;
 
 --for Quartus II environment
-signal p_rom : rom_array;
-attribute ram_init_file : string;
-attribute ram_init_file of p_rom : signal is "sample1-prg.hex";
+--signal p_rom : rom_array;
+--attribute ram_init_file : string;
+--attribute ram_init_file of p_rom : signal is "sample1-prg.hex";
 
 begin
     

diff --git a/de0_cv_nes/mos6502-timing.sdc b/de0_cv_nes/mos6502-timing.sdc
index 688f73d..c0ddea4 100644 (file)
--- a/de0_cv_nes/mos6502-timing.sdc
+++ b/de0_cv_nes/mos6502-timing.sdc
@@ -1,3 +1 @@
 create_clock -name pi_base_clk -period 20 [get_ports {pi_base_clk}]\r
-#create_generated_clock -name cpu_clock -source [get_ports {base_clk}] -divide_by 24 -invert [get_registers {clock_divider:clock_inst|cpu_clk_wk}]\r
-#create_generated_clock -name emu_ppu_clock -source [get_ports {base_clk}] -divide_by 4 -invert [get_registers {clock_divider:clock_inst|counter_register:cpu_clk_cnt|d_flip_flop:counter_reg_inst|q[1]}]\r

diff --git a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
index 1b3607c..71fbb54 100644 (file)
--- a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
+++ b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
@@ -7,11 +7,12 @@ vmap work rtl_work
 \r
 vcom -93 -work work {../../chip_selector.vhd}\r
 vcom -93 -work work {../../mem/ram.vhd}\r
+vcom -93 -work work {../../apu.vhd}\r
 \r
-vcom -93 -work work {../../mem/chr_rom.vhd}\r
-vcom -93 -work work {../../ppu/ppu.vhd}\r
-vcom -93 -work work {../../ppu/render.vhd}\r
-#vcom -93 -work work {../../dummy-ppu.vhd}\r
+#vcom -93 -work work {../../mem/chr_rom.vhd}\r
+#vcom -93 -work work {../../ppu/ppu.vhd}\r
+#vcom -93 -work work {../../ppu/render.vhd}\r
+vcom -93 -work work {../../dummy-ppu.vhd}\r
 \r
 #vcom -93 -work work {../../dummy-mos6502.vhd}\r
 vcom -93 -work work {../../mem/prg_rom.vhd}\r
@@ -59,90 +60,10 @@ add wave -label reg_sp -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/
 #add wave -label reg_tmp_pg_crossed  sim:/testbench_motones_sim/sim_board/cpu_inst/reg_tmp_pg_crossed;\r
 \r
 \r
-#view structure\r
-#view signals\r
-#\r
-#run 25 us\r
-#wave zoom full\r
-#\r
-#run 880 us\r
+#################################### APU part.... ###########################################\r
+add wave -label reg_dma_cur_state   sim:/testbench_motones_sim/sim_board/apu_inst/reg_dma_cur_state;\r
 \r
 \r
-#################################### PPU part.... ###########################################\r
-add wave -divider ppu\r
-add wave -label pi_ce_n         -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/pi_ce_n;\r
-add wave -label ppu_ctrl        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_ctrl;\r
-add wave -label ppu_mask        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_mask;\r
-add wave -label ppu_status      -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/pi_ppu_status;\r
-add wave -label oam_addr        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_oam_addr;\r
-add wave -label oam_data        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_oam_data;\r
-add wave -label ppu_scroll_x    -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_scroll_x;\r
-add wave -label ppu_scroll_y    -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_scroll_y;\r
-add wave -label ppu_addr        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_addr;\r
-add wave -label ppu_data        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_data;\r
-add wave -label reg_v_cur_state            sim:/testbench_motones_sim/sim_board/ppu_inst/reg_v_cur_state;\r
-\r
-add wave -divider vram\r
-add wave -label v_rd_n        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_rd_n;\r
-add wave -label v_wr_n        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_wr_n;\r
-add wave -label vram_addr        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_addr;\r
-add wave -label vram_data        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_data;\r
-\r
-add wave -divider render\r
-#add wave -label vga_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_vga_x;\r
-#add wave -label vga_y       sim:/testbench_motones_sim/sim_board/render_inst/reg_vga_y;\r
-add wave -label nes_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_nes_x;\r
-add wave -label nes_y       sim:/testbench_motones_sim/sim_board/render_inst/reg_nes_y;\r
-\r
-\r
-add wave -divider bg\r
-#add wave -label wr_rnd_en  sim:/testbench_motones_sim/sim_board/wr_rnd_en;\r
-add wave -label reg_v_cur_state sim:/testbench_motones_sim/sim_board/render_inst/reg_v_cur_state;\r
-#add wave -label prf_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_prf_x;\r
-#add wave -label prf_y       sim:/testbench_motones_sim/sim_board/render_inst/reg_prf_y;\r
-\r
-add wave -label disp_nt -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_disp_nt;\r
-add wave -label disp_attr   -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_disp_attr;\r
-add wave -label sft_ptn_l -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_sft_ptn_l;\r
-add wave -label sft_ptn_h -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_sft_ptn_h;\r
-\r
-add wave -divider sprite\r
-add wave -label reg_s_oam_cur_state sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_cur_state;\r
-add wave -label reg_s_oam_ce_n  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_ce_n;\r
-add wave -label reg_s_oam_rd_n  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_rd_n;\r
-add wave -label reg_s_oam_wr_n  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_wr_n;\r
-add wave -label reg_s_oam_addr -radix hex  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_addr;\r
-add wave -label reg_s_oam_data -radix hex  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_data;\r
-\r
-#add wave -label reg_s_oam_cpy_cnt   sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_cpy_cnt;\r
-#add wave -label reg_p_oam_cpy_cnt   sim:/testbench_motones_sim/sim_board/render_inst/reg_p_oam_cpy_cnt;\r
-#add wave -label reg_spr_eval_cnt    sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_eval_cnt;\r
-\r
-add wave -label wr_spr_ce_n  sim:/testbench_motones_sim/sim_board/wr_spr_ce_n;\r
-add wave -label wr_spr_rd_n  sim:/testbench_motones_sim/sim_board/wr_spr_rd_n;\r
-add wave -label wr_spr_wr_n  sim:/testbench_motones_sim/sim_board/wr_spr_wr_n;\r
-add wave -label wr_spr_addr -radix hex  sim:/testbench_motones_sim/sim_board/wr_spr_addr;\r
-add wave -label wr_spr_data -radix hex  sim:/testbench_motones_sim/sim_board/wr_spr_data;\r
-\r
-add wave -label reg_spr_y_tmp -radix hex    sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_y_tmp;\r
-add wave -label reg_spr_tile_tmp -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_tile_tmp;\r
-add wave -label reg_spr_attr -radix hex     sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_attr;\r
-add wave -label reg_spr_x -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_x;\r
-add wave -label reg_spr_ptn_sft_start -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_sft_start;\r
-add wave -label reg_spr_ptn_l -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_l;\r
-add wave -label reg_spr_ptn_h -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_h;\r
-\r
-add wave -divider palette\r
-add wave -label plt_addr -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_plt_addr;\r
-add wave -label plt_data -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_plt_data;\r
-\r
-\r
-add wave -divider vga\r
-add wave -label h_sync_n       sim:/testbench_motones_sim/sim_board/po_h_sync_n;\r
-add wave -label v_sync_n    sim:/testbench_motones_sim/sim_board/po_v_sync_n;\r
-add wave -label r -radix hex sim:/testbench_motones_sim/sim_board/po_r;\r
-add wave -label g -radix hex sim:/testbench_motones_sim/sim_board/po_g;\r
-add wave -label b -radix hex sim:/testbench_motones_sim/sim_board/po_b;\r
 \r
 view structure\r
 view signals\r
@@ -150,5 +71,91 @@ view signals
 run 25 us\r
 wave zoom full\r
 \r
-run 880 us\r
-\r
+run 860 us\r
+\r
+\r
+##################################### PPU part.... ###########################################\r
+#add wave -divider ppu\r
+#add wave -label pi_ce_n         -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/pi_ce_n;\r
+#add wave -label ppu_ctrl        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_ctrl;\r
+#add wave -label ppu_mask        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_mask;\r
+#add wave -label ppu_status      -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/pi_ppu_status;\r
+#add wave -label oam_addr        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_oam_addr;\r
+#add wave -label oam_data        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_oam_data;\r
+#add wave -label ppu_scroll_x    -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_scroll_x;\r
+#add wave -label ppu_scroll_y    -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_scroll_y;\r
+#add wave -label ppu_addr        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_addr;\r
+#add wave -label ppu_data        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_data;\r
+#add wave -label reg_v_cur_state            sim:/testbench_motones_sim/sim_board/ppu_inst/reg_v_cur_state;\r
+#\r
+#add wave -divider vram\r
+#add wave -label v_rd_n        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_rd_n;\r
+#add wave -label v_wr_n        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_wr_n;\r
+#add wave -label vram_addr        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_addr;\r
+#add wave -label vram_data        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_data;\r
+#\r
+#add wave -divider render\r
+##add wave -label vga_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_vga_x;\r
+##add wave -label vga_y       sim:/testbench_motones_sim/sim_board/render_inst/reg_vga_y;\r
+#add wave -label nes_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_nes_x;\r
+#add wave -label nes_y       sim:/testbench_motones_sim/sim_board/render_inst/reg_nes_y;\r
+#\r
+#\r
+#add wave -divider bg\r
+##add wave -label wr_rnd_en  sim:/testbench_motones_sim/sim_board/wr_rnd_en;\r
+#add wave -label reg_v_cur_state sim:/testbench_motones_sim/sim_board/render_inst/reg_v_cur_state;\r
+##add wave -label prf_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_prf_x;\r
+##add wave -label prf_y       sim:/testbench_motones_sim/sim_board/render_inst/reg_prf_y;\r
+#\r
+#add wave -label disp_nt -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_disp_nt;\r
+#add wave -label disp_attr   -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_disp_attr;\r
+#add wave -label sft_ptn_l -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_sft_ptn_l;\r
+#add wave -label sft_ptn_h -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_sft_ptn_h;\r
+#\r
+#add wave -divider sprite\r
+#add wave -label reg_s_oam_cur_state sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_cur_state;\r
+#add wave -label reg_s_oam_ce_n  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_ce_n;\r
+#add wave -label reg_s_oam_rd_n  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_rd_n;\r
+#add wave -label reg_s_oam_wr_n  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_wr_n;\r
+#add wave -label reg_s_oam_addr -radix hex  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_addr;\r
+#add wave -label reg_s_oam_data -radix hex  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_data;\r
+#\r
+##add wave -label reg_s_oam_cpy_cnt   sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_cpy_cnt;\r
+##add wave -label reg_p_oam_cpy_cnt   sim:/testbench_motones_sim/sim_board/render_inst/reg_p_oam_cpy_cnt;\r
+##add wave -label reg_spr_eval_cnt    sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_eval_cnt;\r
+#\r
+#add wave -label wr_spr_ce_n  sim:/testbench_motones_sim/sim_board/wr_spr_ce_n;\r
+#add wave -label wr_spr_rd_n  sim:/testbench_motones_sim/sim_board/wr_spr_rd_n;\r
+#add wave -label wr_spr_wr_n  sim:/testbench_motones_sim/sim_board/wr_spr_wr_n;\r
+#add wave -label wr_spr_addr -radix hex  sim:/testbench_motones_sim/sim_board/wr_spr_addr;\r
+#add wave -label wr_spr_data -radix hex  sim:/testbench_motones_sim/sim_board/wr_spr_data;\r
+#\r
+#add wave -label reg_spr_y_tmp -radix hex    sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_y_tmp;\r
+#add wave -label reg_spr_tile_tmp -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_tile_tmp;\r
+#add wave -label reg_spr_attr -radix hex     sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_attr;\r
+#add wave -label reg_spr_x -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_x;\r
+#add wave -label reg_spr_ptn_sft_start -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_sft_start;\r
+#add wave -label reg_spr_ptn_l -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_l;\r
+#add wave -label reg_spr_ptn_h -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_h;\r
+#\r
+#add wave -divider palette\r
+#add wave -label plt_addr -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_plt_addr;\r
+#add wave -label plt_data -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_plt_data;\r
+#\r
+#\r
+#add wave -divider vga\r
+#add wave -label h_sync_n       sim:/testbench_motones_sim/sim_board/po_h_sync_n;\r
+#add wave -label v_sync_n    sim:/testbench_motones_sim/sim_board/po_v_sync_n;\r
+#add wave -label r -radix hex sim:/testbench_motones_sim/sim_board/po_r;\r
+#add wave -label g -radix hex sim:/testbench_motones_sim/sim_board/po_g;\r
+#add wave -label b -radix hex sim:/testbench_motones_sim/sim_board/po_b;\r
+#\r
+#view structure\r
+#view signals\r
+#\r
+#run 25 us\r
+#wave zoom full\r
+#\r
+#run 880 us\r
+#\r
+#
\ No newline at end of file

diff --git a/tools/regression-test/regression.asm b/tools/regression-test/regression.asm
index 55ffd14..9c851ce 100644 (file)
--- a/tools/regression-test/regression.asm
+++ b/tools/regression-test/regression.asm
@@ -32,19 +32,19 @@
     \r
     jsr init_global\r
     jsr init_ppu\r
-\r
-    lda ad_start_msg\r
-    sta $00\r
-    lda ad_start_msg+1\r
-    sta $01\r
-    jsr print_ln\r
-;;    jsr print_ln\r
-;;    jsr print_ln\r
-;;    jsr print_ln\r
-;;    jsr print_ln\r
-;;    jsr print_ln\r
-;;\r
-;;    ;;test start...\r
+;\r
+;    lda ad_start_msg\r
+;    sta $00\r
+;    lda ad_start_msg+1\r
+;    sta $01\r
+;    jsr print_ln\r
+;    jsr print_ln\r
+;    jsr print_ln\r
+;    jsr print_ln\r
+;    jsr print_ln\r
+;    jsr print_ln\r
+;\r
+;    ;;test start...\r
 ;    jsr addr_test\r
 ;    jsr single_inst_test\r
 ;    jsr a2_inst_test\r
@@ -57,7 +57,7 @@
 ;    jsr pg_border_test\r
 ;    jsr dma_test\r
 ;\r
-;    jsr simple_dma_test\r
+    jsr simple_dma_test\r
 \r
 .endproc\r
 \r