dmaengine: ste_dma40: reset priority bit for logical channels

This patch sets the SSCFG/SDCFG bit[7] PRI only for physical channel
requests with high priority.  For logical channels, this bit will be
zero.

Signed-off-by: Narayanan G <narayanan.gopalakrishnan@stericsson.com>
Reviewed-by: Rabin Vincent <rabin.vincent@stericsson.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Fabio Baltieri <fabio.baltieri@linaro.org>

diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
index 851ad56..d64b72a 100644 (file)
--- a/drivers/dma/ste_dma40_ll.c
+++ b/drivers/dma/ste_dma40_ll.c
@@ -102,17 +102,18 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
                src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
                dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;
 
+               /* Set the priority bit to high for the physical channel */
+               if (cfg->high_priority) {
+                       src |= 1 << D40_SREG_CFG_PRI_POS;
+                       dst |= 1 << D40_SREG_CFG_PRI_POS;
+               }
+
        } else {
                /* Logical channel */
                dst |= 1 << D40_SREG_CFG_LOG_GIM_POS;
                src |= 1 << D40_SREG_CFG_LOG_GIM_POS;
        }
 
-       if (cfg->high_priority) {
-               src |= 1 << D40_SREG_CFG_PRI_POS;
-               dst |= 1 << D40_SREG_CFG_PRI_POS;
-       }
-
        if (cfg->src_info.big_endian)
                src |= 1 << D40_SREG_CFG_LBE_POS;
        if (cfg->dst_info.big_endian)