let NumMicroOps = 23;
let ResourceCycles = [1,5,3,4,10];
}
-def: InstRW<[BWWriteResGroup191], (instregex "IN32ri")>;
-def: InstRW<[BWWriteResGroup191], (instregex "IN32rr")>;
+def: InstRW<[BWWriteResGroup191], (instregex "IN(16|32)ri")>;
+def: InstRW<[BWWriteResGroup191], (instregex "IN(16|32)rr")>;
def: InstRW<[BWWriteResGroup191], (instregex "IN8ri")>;
def: InstRW<[BWWriteResGroup191], (instregex "IN8rr")>;
let NumMicroOps = 23;
let ResourceCycles = [1,5,2,1,4,10];
}
-def: InstRW<[BWWriteResGroup194], (instregex "OUT32ir")>;
-def: InstRW<[BWWriteResGroup194], (instregex "OUT32rr")>;
+def: InstRW<[BWWriteResGroup194], (instregex "OUT(16|32)ir")>;
+def: InstRW<[BWWriteResGroup194], (instregex "OUT(16|32)rr")>;
def: InstRW<[BWWriteResGroup194], (instregex "OUT8ir")>;
def: InstRW<[BWWriteResGroup194], (instregex "OUT8rr")>;
let NumMicroOps = 23;
let ResourceCycles = [1,5,3,4,10];
}
-def: InstRW<[HWWriteResGroup170], (instregex "IN32ri")>;
-def: InstRW<[HWWriteResGroup170], (instregex "IN32rr")>;
+def: InstRW<[HWWriteResGroup170], (instregex "IN(16|32)ri")>;
+def: InstRW<[HWWriteResGroup170], (instregex "IN(16|32)rr")>;
def: InstRW<[HWWriteResGroup170], (instregex "IN8ri")>;
def: InstRW<[HWWriteResGroup170], (instregex "IN8rr")>;
let NumMicroOps = 23;
let ResourceCycles = [1,5,2,1,4,10];
}
-def: InstRW<[HWWriteResGroup171], (instregex "OUT32ir")>;
-def: InstRW<[HWWriteResGroup171], (instregex "OUT32rr")>;
+def: InstRW<[HWWriteResGroup171], (instregex "OUT(16|32)ir")>;
+def: InstRW<[HWWriteResGroup171], (instregex "OUT(16|32)rr")>;
def: InstRW<[HWWriteResGroup171], (instregex "OUT8ir")>;
def: InstRW<[HWWriteResGroup171], (instregex "OUT8rr")>;
let NumMicroOps = 23;
let ResourceCycles = [1,5,3,4,10];
}
-def: InstRW<[SKLWriteResGroup209], (instregex "IN32ri")>;
-def: InstRW<[SKLWriteResGroup209], (instregex "IN32rr")>;
+def: InstRW<[SKLWriteResGroup209], (instregex "IN(16|32)ri")>;
+def: InstRW<[SKLWriteResGroup209], (instregex "IN(16|32)rr")>;
def: InstRW<[SKLWriteResGroup209], (instregex "IN8ri")>;
def: InstRW<[SKLWriteResGroup209], (instregex "IN8rr")>;
let NumMicroOps = 23;
let ResourceCycles = [1,5,2,1,4,10];
}
-def: InstRW<[SKLWriteResGroup210], (instregex "OUT32ir")>;
-def: InstRW<[SKLWriteResGroup210], (instregex "OUT32rr")>;
+def: InstRW<[SKLWriteResGroup210], (instregex "OUT(16|32)ir")>;
+def: InstRW<[SKLWriteResGroup210], (instregex "OUT(16|32)rr")>;
def: InstRW<[SKLWriteResGroup210], (instregex "OUT8ir")>;
def: InstRW<[SKLWriteResGroup210], (instregex "OUT8rr")>;
let NumMicroOps = 23;
let ResourceCycles = [1,5,3,4,10];
}
-def: InstRW<[SKXWriteResGroup247], (instregex "IN32ri")>;
-def: InstRW<[SKXWriteResGroup247], (instregex "IN32rr")>;
+def: InstRW<[SKXWriteResGroup247], (instregex "IN(16|32)ri")>;
+def: InstRW<[SKXWriteResGroup247], (instregex "IN(16|32)rr")>;
def: InstRW<[SKXWriteResGroup247], (instregex "IN8ri")>;
def: InstRW<[SKXWriteResGroup247], (instregex "IN8rr")>;
let NumMicroOps = 23;
let ResourceCycles = [1,5,2,1,4,10];
}
-def: InstRW<[SKXWriteResGroup248], (instregex "OUT32ir")>;
-def: InstRW<[SKXWriteResGroup248], (instregex "OUT32rr")>;
+def: InstRW<[SKXWriteResGroup248], (instregex "OUT(16|32)ir")>;
+def: InstRW<[SKXWriteResGroup248], (instregex "OUT(16|32)rr")>;
def: InstRW<[SKXWriteResGroup248], (instregex "OUT8ir")>;
def: InstRW<[SKXWriteResGroup248], (instregex "OUT8rr")>;