clk: mediatek: clk-mt8192: Add clock mux notifier for mfg_pll_sel

Following the changes that were done for mt8183, add a clock notifier
for the GPU PLL selector mux: this allows safe clock rate changes by
temporarily reparenting the GPU to a safe clock (clk26m) while the
MFGPLL is reprogrammed and stabilizes.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20220927101128.44758-11-angelogioacchino.delregno@collabora.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>

diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c
index ebbd279..187dbff 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8192.c
+++ b/drivers/clk/mediatek/clk-mt8192.c
@@ -1224,6 +1224,28 @@ static void clk_mt8192_top_init_early(struct device_node *node)
 CLK_OF_DECLARE_DRIVER(mt8192_topckgen, "mediatek,mt8192-topckgen",
                      clk_mt8192_top_init_early);
 
+/* Register mux notifier for MFG mux */
+static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
+{
+       struct mtk_mux_nb *mfg_mux_nb;
+       int i;
+
+       mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL);
+       if (!mfg_mux_nb)
+               return -ENOMEM;
+
+       for (i = 0; i < ARRAY_SIZE(top_mtk_muxes); i++)
+               if (top_mtk_muxes[i].id == CLK_TOP_MFG_PLL_SEL)
+                       break;
+       if (i == ARRAY_SIZE(top_mtk_muxes))
+               return -EINVAL;
+
+       mfg_mux_nb->ops = top_mtk_muxes[i].ops;
+       mfg_mux_nb->bypass_index = 0; /* Bypass to 26M crystal */
+
+       return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb);
+}
+
 static int clk_mt8192_top_probe(struct platform_device *pdev)
 {
        struct device_node *node = pdev->dev.of_node;
@@ -1247,6 +1269,12 @@ static int clk_mt8192_top_probe(struct platform_device *pdev)
        if (r)
                return r;
 
+       r = clk_mt8192_reg_mfg_mux_notifier(&pdev->dev,
+                                           top_clk_data->hws[CLK_TOP_MFG_PLL_SEL]->clk);
+       if (r)
+               return r;
+
+
        return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
                                      top_clk_data);
 }