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pinctrl: renesas: r8a779g0: Remove unused IPxSRx definitions
authorKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Fri, 1 Jul 2022 01:37:12 +0000 (01:37 +0000)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 5 Jul 2022 07:12:36 +0000 (09:12 +0200)
Current R-Car V4H PFC code has many IPxSRx definitions with all 0.
But these have no meaning.  This patch removes them.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/877d4xtxyv.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/pinctrl/renesas/pfc-r8a779g0.c patch | blob | history

diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index 007319d..f14834b 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -286,11 +286,6 @@
 #define IP2SR0_3_0     FM(MSIOF2_TXD)          FM(HCTS1_N)             FM(CTS1_N)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP2SR0_7_4     FM(MSIOF2_SCK)          FM(HRTS1_N)             FM(RTS1_N)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP2SR0_11_8    FM(MSIOF2_RXD)          FM(HSCK1)               FM(SCK1)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR0_15_12   F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR0_19_16   F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR0_23_20   F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR0_27_24   F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR0_31_28   F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 
 /* SR1 */
 /* IP0SR1 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
@@ -329,9 +324,6 @@
 #define IP3SR1_11_8    FM(HRTS3_N)             FM(RTS3_N)              FM(MSIOF4_TXD)  F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP3SR1_15_12   FM(HCTS3_N)             FM(RX3)                 FM(MSIOF4_RXD)  F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP3SR1_19_16   FM(HTX3)                FM(TX3)                 FM(MSIOF4_SYNC) F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_23_20   F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_27_24   F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_31_28   F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 
 /* SR2 */
 /* IP0SR2 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
@@ -359,10 +351,6 @@
 #define IP2SR2_7_4     FM(CANFD4_RX)           F_(0, 0)                FM(PWM5)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP2SR2_11_8    FM(CANFD7_TX)           F_(0, 0)                FM(PWM6)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP2SR2_15_12   FM(CANFD7_RX)           F_(0, 0)                FM(PWM7)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR2_19_16   F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR2_23_20   F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR2_27_24   F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR2_31_28   F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 
 /* SR3 */
 /* IP0SR3 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
@@ -402,8 +390,6 @@
 #define IP3SR3_15_12   FM(RPC_RESET_N)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP3SR3_19_16   FM(RPC_WP_N)            F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP3SR3_23_20   FM(RPC_INT_N)           F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR3_27_24   F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR3_31_28   F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 
 /* SR6 */
 /* IP0SR6 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
@@ -432,9 +418,6 @@
 #define IP2SR6_11_8    FM(AVB1_TD3)            FM(AVB1_MII_TD3)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP2SR6_15_12   FM(AVB1_RD3)            FM(AVB1_MII_RD3)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP2SR6_19_16   FM(AVB1_TXCREFCLK)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR6_23_20   F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR6_27_24   F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR6_31_28   F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 
 /* SR7 */
 /* IP0SR7 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
@@ -463,9 +446,6 @@
 #define IP2SR7_11_8    FM(AVB0_RD0)            FM(AVB0_MII_RD0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP2SR7_15_12   FM(AVB0_RXC)            FM(AVB0_MII_RXC)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP2SR7_19_16   FM(AVB0_RX_CTL)         FM(AVB0_MII_RX_DV)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR7_23_20   F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR7_27_24   F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR7_31_28   F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 
 /* SR8 */
 /* IP0SR8 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
@@ -485,9 +465,6 @@
 #define IP1SR8_15_12   FM(SDA5)                FM(SCIF_CLK2)           F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1SR8_19_16   F_(0, 0)                FM(HCTS2_N)             FM(TX4)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1SR8_23_20   F_(0, 0)                FM(HSCK2)               FM(RX4)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR8_27_24   F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR8_31_28   F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
 
 #define PINMUX_GPSR    \
                                                GPSR3_29                                                                                        \
@@ -526,29 +503,29 @@ GPSR0_0           GPSR1_0         GPSR2_0         GPSR3_0         GPSR4_0         GPSR5_0         GPSR6_0         GPSR7_0         GPSR8_0
 FM(IP0SR0_3_0)         IP0SR0_3_0      FM(IP1SR0_3_0)          IP1SR0_3_0      FM(IP2SR0_3_0)          IP2SR0_3_0      \
 FM(IP0SR0_7_4)         IP0SR0_7_4      FM(IP1SR0_7_4)          IP1SR0_7_4      FM(IP2SR0_7_4)          IP2SR0_7_4      \
 FM(IP0SR0_11_8)                IP0SR0_11_8     FM(IP1SR0_11_8)         IP1SR0_11_8     FM(IP2SR0_11_8)         IP2SR0_11_8     \
-FM(IP0SR0_15_12)       IP0SR0_15_12    FM(IP1SR0_15_12)        IP1SR0_15_12    FM(IP2SR0_15_12)        IP2SR0_15_12    \
-FM(IP0SR0_19_16)       IP0SR0_19_16    FM(IP1SR0_19_16)        IP1SR0_19_16    FM(IP2SR0_19_16)        IP2SR0_19_16    \
-FM(IP0SR0_23_20)       IP0SR0_23_20    FM(IP1SR0_23_20)        IP1SR0_23_20    FM(IP2SR0_23_20)        IP2SR0_23_20    \
-FM(IP0SR0_27_24)       IP0SR0_27_24    FM(IP1SR0_27_24)        IP1SR0_27_24    FM(IP2SR0_27_24)        IP2SR0_27_24    \
-FM(IP0SR0_31_28)       IP0SR0_31_28    FM(IP1SR0_31_28)        IP1SR0_31_28    FM(IP2SR0_31_28)        IP2SR0_31_28    \
+FM(IP0SR0_15_12)       IP0SR0_15_12    FM(IP1SR0_15_12)        IP1SR0_15_12    \
+FM(IP0SR0_19_16)       IP0SR0_19_16    FM(IP1SR0_19_16)        IP1SR0_19_16    \
+FM(IP0SR0_23_20)       IP0SR0_23_20    FM(IP1SR0_23_20)        IP1SR0_23_20    \
+FM(IP0SR0_27_24)       IP0SR0_27_24    FM(IP1SR0_27_24)        IP1SR0_27_24    \
+FM(IP0SR0_31_28)       IP0SR0_31_28    FM(IP1SR0_31_28)        IP1SR0_31_28    \
 \
 FM(IP0SR1_3_0)         IP0SR1_3_0      FM(IP1SR1_3_0)          IP1SR1_3_0      FM(IP2SR1_3_0)          IP2SR1_3_0      FM(IP3SR1_3_0)          IP3SR1_3_0      \
 FM(IP0SR1_7_4)         IP0SR1_7_4      FM(IP1SR1_7_4)          IP1SR1_7_4      FM(IP2SR1_7_4)          IP2SR1_7_4      FM(IP3SR1_7_4)          IP3SR1_7_4      \
 FM(IP0SR1_11_8)                IP0SR1_11_8     FM(IP1SR1_11_8)         IP1SR1_11_8     FM(IP2SR1_11_8)         IP2SR1_11_8     FM(IP3SR1_11_8)         IP3SR1_11_8     \
 FM(IP0SR1_15_12)       IP0SR1_15_12    FM(IP1SR1_15_12)        IP1SR1_15_12    FM(IP2SR1_15_12)        IP2SR1_15_12    FM(IP3SR1_15_12)        IP3SR1_15_12    \
 FM(IP0SR1_19_16)       IP0SR1_19_16    FM(IP1SR1_19_16)        IP1SR1_19_16    FM(IP2SR1_19_16)        IP2SR1_19_16    FM(IP3SR1_19_16)        IP3SR1_19_16    \
-FM(IP0SR1_23_20)       IP0SR1_23_20    FM(IP1SR1_23_20)        IP1SR1_23_20    FM(IP2SR1_23_20)        IP2SR1_23_20    FM(IP3SR1_23_20)        IP3SR1_23_20    \
-FM(IP0SR1_27_24)       IP0SR1_27_24    FM(IP1SR1_27_24)        IP1SR1_27_24    FM(IP2SR1_27_24)        IP2SR1_27_24    FM(IP3SR1_27_24)        IP3SR1_27_24    \
-FM(IP0SR1_31_28)       IP0SR1_31_28    FM(IP1SR1_31_28)        IP1SR1_31_28    FM(IP2SR1_31_28)        IP2SR1_31_28    FM(IP3SR1_31_28)        IP3SR1_31_28    \
+FM(IP0SR1_23_20)       IP0SR1_23_20    FM(IP1SR1_23_20)        IP1SR1_23_20    FM(IP2SR1_23_20)        IP2SR1_23_20    \
+FM(IP0SR1_27_24)       IP0SR1_27_24    FM(IP1SR1_27_24)        IP1SR1_27_24    FM(IP2SR1_27_24)        IP2SR1_27_24    \
+FM(IP0SR1_31_28)       IP0SR1_31_28    FM(IP1SR1_31_28)        IP1SR1_31_28    FM(IP2SR1_31_28)        IP2SR1_31_28    \
 \
 FM(IP0SR2_3_0)         IP0SR2_3_0      FM(IP1SR2_3_0)          IP1SR2_3_0      FM(IP2SR2_3_0)          IP2SR2_3_0      \
 FM(IP0SR2_7_4)         IP0SR2_7_4      FM(IP1SR2_7_4)          IP1SR2_7_4      FM(IP2SR2_7_4)          IP2SR2_7_4      \
 FM(IP0SR2_11_8)                IP0SR2_11_8     FM(IP1SR2_11_8)         IP1SR2_11_8     FM(IP2SR2_11_8)         IP2SR2_11_8     \
 FM(IP0SR2_15_12)       IP0SR2_15_12    FM(IP1SR2_15_12)        IP1SR2_15_12    FM(IP2SR2_15_12)        IP2SR2_15_12    \
-FM(IP0SR2_19_16)       IP0SR2_19_16    FM(IP1SR2_19_16)        IP1SR2_19_16    FM(IP2SR2_19_16)        IP2SR2_19_16    \
-FM(IP0SR2_23_20)       IP0SR2_23_20    FM(IP1SR2_23_20)        IP1SR2_23_20    FM(IP2SR2_23_20)        IP2SR2_23_20    \
-FM(IP0SR2_27_24)       IP0SR2_27_24    FM(IP1SR2_27_24)        IP1SR2_27_24    FM(IP2SR2_27_24)        IP2SR2_27_24    \
-FM(IP0SR2_31_28)       IP0SR2_31_28    FM(IP1SR2_31_28)        IP1SR2_31_28    FM(IP2SR2_31_28)        IP2SR2_31_28    \
+FM(IP0SR2_19_16)       IP0SR2_19_16    FM(IP1SR2_19_16)        IP1SR2_19_16    \
+FM(IP0SR2_23_20)       IP0SR2_23_20    FM(IP1SR2_23_20)        IP1SR2_23_20    \
+FM(IP0SR2_27_24)       IP0SR2_27_24    FM(IP1SR2_27_24)        IP1SR2_27_24    \
+FM(IP0SR2_31_28)       IP0SR2_31_28    FM(IP1SR2_31_28)        IP1SR2_31_28    \
 \
 FM(IP0SR3_3_0)         IP0SR3_3_0      FM(IP1SR3_3_0)          IP1SR3_3_0      FM(IP2SR3_3_0)          IP2SR3_3_0      FM(IP3SR3_3_0)          IP3SR3_3_0      \
 FM(IP0SR3_7_4)         IP0SR3_7_4      FM(IP1SR3_7_4)          IP1SR3_7_4      FM(IP2SR3_7_4)          IP2SR3_7_4      FM(IP3SR3_7_4)          IP3SR3_7_4      \
@@ -556,26 +533,26 @@ FM(IP0SR3_11_8)           IP0SR3_11_8     FM(IP1SR3_11_8)         IP1SR3_11_8     FM(IP2SR3_11_8)         IP2SR
 FM(IP0SR3_15_12)       IP0SR3_15_12    FM(IP1SR3_15_12)        IP1SR3_15_12    FM(IP2SR3_15_12)        IP2SR3_15_12    FM(IP3SR3_15_12)        IP3SR3_15_12    \
 FM(IP0SR3_19_16)       IP0SR3_19_16    FM(IP1SR3_19_16)        IP1SR3_19_16    FM(IP2SR3_19_16)        IP2SR3_19_16    FM(IP3SR3_19_16)        IP3SR3_19_16    \
 FM(IP0SR3_23_20)       IP0SR3_23_20    FM(IP1SR3_23_20)        IP1SR3_23_20    FM(IP2SR3_23_20)        IP2SR3_23_20    FM(IP3SR3_23_20)        IP3SR3_23_20    \
-FM(IP0SR3_27_24)       IP0SR3_27_24    FM(IP1SR3_27_24)        IP1SR3_27_24    FM(IP2SR3_27_24)        IP2SR3_27_24    FM(IP3SR3_27_24)        IP3SR3_27_24    \
-FM(IP0SR3_31_28)       IP0SR3_31_28    FM(IP1SR3_31_28)        IP1SR3_31_28    FM(IP2SR3_31_28)        IP2SR3_31_28    FM(IP3SR3_31_28)        IP3SR3_31_28    \
+FM(IP0SR3_27_24)       IP0SR3_27_24    FM(IP1SR3_27_24)        IP1SR3_27_24    FM(IP2SR3_27_24)        IP2SR3_27_24                                            \
+FM(IP0SR3_31_28)       IP0SR3_31_28    FM(IP1SR3_31_28)        IP1SR3_31_28    FM(IP2SR3_31_28)        IP2SR3_31_28                                            \
 \
 FM(IP0SR6_3_0)         IP0SR6_3_0      FM(IP1SR6_3_0)          IP1SR6_3_0      FM(IP2SR6_3_0)          IP2SR6_3_0      \
 FM(IP0SR6_7_4)         IP0SR6_7_4      FM(IP1SR6_7_4)          IP1SR6_7_4      FM(IP2SR6_7_4)          IP2SR6_7_4      \
 FM(IP0SR6_11_8)                IP0SR6_11_8     FM(IP1SR6_11_8)         IP1SR6_11_8     FM(IP2SR6_11_8)         IP2SR6_11_8     \
 FM(IP0SR6_15_12)       IP0SR6_15_12    FM(IP1SR6_15_12)        IP1SR6_15_12    FM(IP2SR6_15_12)        IP2SR6_15_12    \
 FM(IP0SR6_19_16)       IP0SR6_19_16    FM(IP1SR6_19_16)        IP1SR6_19_16    FM(IP2SR6_19_16)        IP2SR6_19_16    \
-FM(IP0SR6_23_20)       IP0SR6_23_20    FM(IP1SR6_23_20)        IP1SR6_23_20    FM(IP2SR6_23_20)        IP2SR6_23_20    \
-FM(IP0SR6_27_24)       IP0SR6_27_24    FM(IP1SR6_27_24)        IP1SR6_27_24    FM(IP2SR6_27_24)        IP2SR6_27_24    \
-FM(IP0SR6_31_28)       IP0SR6_31_28    FM(IP1SR6_31_28)        IP1SR6_31_28    FM(IP2SR6_31_28)        IP2SR6_31_28    \
+FM(IP0SR6_23_20)       IP0SR6_23_20    FM(IP1SR6_23_20)        IP1SR6_23_20    \
+FM(IP0SR6_27_24)       IP0SR6_27_24    FM(IP1SR6_27_24)        IP1SR6_27_24    \
+FM(IP0SR6_31_28)       IP0SR6_31_28    FM(IP1SR6_31_28)        IP1SR6_31_28    \
 \
 FM(IP0SR7_3_0)         IP0SR7_3_0      FM(IP1SR7_3_0)          IP1SR7_3_0      FM(IP2SR7_3_0)          IP2SR7_3_0      \
 FM(IP0SR7_7_4)         IP0SR7_7_4      FM(IP1SR7_7_4)          IP1SR7_7_4      FM(IP2SR7_7_4)          IP2SR7_7_4      \
 FM(IP0SR7_11_8)                IP0SR7_11_8     FM(IP1SR7_11_8)         IP1SR7_11_8     FM(IP2SR7_11_8)         IP2SR7_11_8     \
 FM(IP0SR7_15_12)       IP0SR7_15_12    FM(IP1SR7_15_12)        IP1SR7_15_12    FM(IP2SR7_15_12)        IP2SR7_15_12    \
 FM(IP0SR7_19_16)       IP0SR7_19_16    FM(IP1SR7_19_16)        IP1SR7_19_16    FM(IP2SR7_19_16)        IP2SR7_19_16    \
-FM(IP0SR7_23_20)       IP0SR7_23_20    FM(IP1SR7_23_20)        IP1SR7_23_20    FM(IP2SR7_23_20)        IP2SR7_23_20    \
-FM(IP0SR7_27_24)       IP0SR7_27_24    FM(IP1SR7_27_24)        IP1SR7_27_24    FM(IP2SR7_27_24)        IP2SR7_27_24    \
-FM(IP0SR7_31_28)       IP0SR7_31_28    FM(IP1SR7_31_28)        IP1SR7_31_28    FM(IP2SR7_31_28)        IP2SR7_31_28    \
+FM(IP0SR7_23_20)       IP0SR7_23_20    FM(IP1SR7_23_20)        IP1SR7_23_20    \
+FM(IP0SR7_27_24)       IP0SR7_27_24    FM(IP1SR7_27_24)        IP1SR7_27_24    \
+FM(IP0SR7_31_28)       IP0SR7_31_28    FM(IP1SR7_31_28)        IP1SR7_31_28    \
 \
 FM(IP0SR8_3_0)         IP0SR8_3_0      FM(IP1SR8_3_0)          IP1SR8_3_0      \
 FM(IP0SR8_7_4)         IP0SR8_7_4      FM(IP1SR8_7_4)          IP1SR8_7_4      \
@@ -583,8 +560,8 @@ FM(IP0SR8_11_8)             IP0SR8_11_8     FM(IP1SR8_11_8)         IP1SR8_11_8     \
 FM(IP0SR8_15_12)       IP0SR8_15_12    FM(IP1SR8_15_12)        IP1SR8_15_12    \
 FM(IP0SR8_19_16)       IP0SR8_19_16    FM(IP1SR8_19_16)        IP1SR8_19_16    \
 FM(IP0SR8_23_20)       IP0SR8_23_20    FM(IP1SR8_23_20)        IP1SR8_23_20    \
-FM(IP0SR8_27_24)       IP0SR8_27_24    FM(IP1SR8_27_24)        IP1SR8_27_24    \
-FM(IP0SR8_31_28)       IP0SR8_31_28    FM(IP1SR8_31_28)        IP1SR8_31_28
+FM(IP0SR8_27_24)       IP0SR8_27_24    \
+FM(IP0SR8_31_28)       IP0SR8_31_28
 
 /* MOD_SEL4 */                 /* 0 */                         /* 1 */
 #define MOD_SEL4_19            FM(SEL_TSN0_TD2_0)              FM(SEL_TSN0_TD2_1)
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