signal dbg_s_oam_ce_rn_wn : out std_logic_vector (2 downto 0);
signal dbg_s_oam_addr : out std_logic_vector (4 downto 0);
signal dbg_s_oam_data : out std_logic_vector (7 downto 0);
+ signal dbg_s_oam_addr_cpy : out std_logic_vector (4 downto 0);\r
dl_cpu_clk : in std_logic;\r
ppu_clk : in std_logic;\r
signal dbg_s_oam_ce_rn_wn : std_logic_vector (2 downto 0);
signal dbg_s_oam_addr : std_logic_vector (4 downto 0);
signal dbg_s_oam_data : std_logic_vector (7 downto 0);
+ signal dbg_s_oam_addr_cpy : std_logic_vector (4 downto 0);\r
signal dbg_ppu_data_dummy : std_logic_vector (7 downto 0);
signal dbg_ppu_status_dummy : std_logic_vector (7 downto 0);
signal dbg_ppu_scrl_x_dummy : std_logic_vector (7 downto 0);
dbg_exec_cycle_dummy,
dbg_ea_carry,
dbg_status_dummy,
- dbg_pcl, dbg_pch, dbg_sp_dummy, dbg_x_dummy, dbg_y_dummy, dbg_acc,
+ dbg_pcl, dbg_pch, dbg_sp_dummy, dbg_x_dummy, dbg_y_dummy, dbg_acc_dummy,
dbg_dec_oe_n,
dbg_dec_val_dummy,
dbg_stat_we_n ,
dbg_s_oam_ce_rn_wn ,
dbg_s_oam_addr ,
dbg_s_oam_data ,
+ dbg_s_oam_addr_cpy ,\r
cpu_mem_clk ,\r
ppu_clk ,
dbg_int_d_bus(4 downto 0) <= dbg_s_oam_addr(4 downto 0);\r
dbg_dec_val <= dbg_s_oam_data;\r
dbg_y(5 downto 0) <= dbg_vga_y(5 downto 0);\r
+ dbg_acc <= "000" & dbg_s_oam_addr_cpy;\r
--dbg_ppu_scrl_y <= dbg_ppu_scrl_y_dummy;\r
\r
--nmi_n <= dummy_nmi;\r
signal dbg_s_oam_ce_rn_wn : out std_logic_vector (2 downto 0);
signal dbg_s_oam_addr : out std_logic_vector (4 downto 0);
signal dbg_s_oam_data : out std_logic_vector (7 downto 0);
+ signal dbg_s_oam_addr_cpy : out std_logic_vector (4 downto 0);
dl_cpu_clk : in std_logic;
ppu_clk : in std_logic;
signal dbg_s_oam_ce_rn_wn : out std_logic_vector (2 downto 0);
signal dbg_s_oam_addr : out std_logic_vector (4 downto 0);
signal dbg_s_oam_data : out std_logic_vector (7 downto 0);
+ signal dbg_s_oam_addr_cpy : out std_logic_vector (4 downto 0);
vga_clk : in std_logic;
emu_ppu_clk : in std_logic;
dbg_s_oam_ce_rn_wn ,
dbg_s_oam_addr ,
dbg_s_oam_data ,
-
+ dbg_s_oam_addr_cpy ,
+
vga_clk, emu_ppu_clk, emu_ppu_clk_dl, rst_n,
rnd_rd_n, rnd_wr_n, rnd_ale_n, rnd_vram_addr, rnd_vram_data,
h_sync_n, v_sync_n, r, g, b,
signal dbg_s_oam_ce_rn_wn : out std_logic_vector (2 downto 0);\r
signal dbg_s_oam_addr : out std_logic_vector (4 downto 0);\r
signal dbg_s_oam_data : out std_logic_vector (7 downto 0);\r
- signal dbg_emu_ppu_clk : out std_logic;\r
+ signal dbg_s_oam_addr_cpy : out std_logic_vector (4 downto 0);\r
\r
vga_clk : in std_logic;\r
emu_ppu_clk : in std_logic;\r
dbg_s_oam_ce_rn_wn <= s_oam_ram_ce_n & s_oam_r_n & s_oam_w_n;\r
dbg_s_oam_addr <= s_oam_addr;\r
dbg_s_oam_data <= s_oam_data;\r
-\r
+ dbg_s_oam_addr_cpy <= s_oam_addr_cpy;\r
-- dbg_disp_nt <= disp_nt;\r
-- dbg_disp_attr <= disp_attr;\r
-- dbg_disp_ptn_h <= disp_ptn_h;\r
-- dbg_disp_ptn_l <= disp_ptn_l;\r
dbg_disp_nt <= spr_tile_tmp;\r
dbg_disp_attr <= spr_attr(0);\r
- dbg_disp_ptn_h <= spr_ptn_h(0) & "00000000";\r
- dbg_disp_ptn_l <= spr_ptn_l(0) & "00000000";\r
+ dbg_disp_ptn_h <= "00000000" & spr_ptn_h(0);\r
+ dbg_disp_ptn_l <= "00000000" & spr_ptn_l(0);\r
\r
\r
-----------------------------------------\r
\r
add wave -divider ppu_render\r
#add wave -label misc_we_n -radix hex {sim:/testbench_motones_sim/sim_board/dbg_y(5 downto 0)}\r
+add wave -label dbg_s_oam_addr_cpy -radix decimal sim:/testbench_motones_sim/sim_board/dbg_acc\r
add wave -label dbg_disp_nt -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_nt\r
add wave -label dbg_disp_attr -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_attr\r
-add wave -label dbg_disp_ptn_h -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h\r
add wave -label dbg_disp_ptn_l -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_l\r
+add wave -label dbg_disp_ptn_h -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h\r
\r
#add wave -divider vga_out\r
#add wave -label h_sync_n sim:/testbench_motones_sim/sim_board/v_sync_n\r