"syscall"
*am33
{
- unsigned int sp, next_pc;
+ unsigned32 sp, next_pc;
PC = cia;
sp = State.regs[REG_SP];
"movm"
*am33
{
- unsigned long usp = State.regs[REG_USP];
- unsigned long mask;
+ unsigned32 usp = State.regs[REG_USP];
+ unsigned32 mask;
PC = cia;
mask = REGS;
"movm"
*am33
{
- unsigned long usp = State.regs[REG_USP];
- unsigned long mask;
+ unsigned32 usp = State.regs[REG_USP];
+ unsigned32 mask;
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
{
{
int srcreg, dstreg;
int z, c, n, v;
- unsigned long reg1, reg2, sum;
+ unsigned32 reg1, reg2, sum;
PC = cia;
srcreg = translate_rreg (SD_, RM2);
{
int srcreg, dstreg;
int z, c, n, v;
- unsigned long reg1, reg2, difference;
+ unsigned32 reg1, reg2, difference;
PC = cia;
srcreg = translate_rreg (SD_, RM2);
*am33
{
int srcreg, dstreg;
- long temp;
+ signed32 temp;
int c, z, n;
PC = cia;
{
int dstreg;
int c, n, z;
- unsigned long value;
+ unsigned32 value;
PC = cia;
dstreg = translate_rreg (SD_, RN0);
{
int dstreg;
int c, n, z;
- unsigned long value;
+ unsigned32 value;
PC = cia;
dstreg = translate_rreg (SD_, RN0);
*am33
{
int srcreg, dstreg;
- unsigned long long temp;
+ unsigned64 temp;
int n, z;
PC = cia;
*am33
{
int srcreg, dstreg;
- unsigned long long temp;
+ unsigned64 temp;
int n, z;
PC = cia;
*am33
{
int srcreg, dstreg;
- long long temp;
+ signed64 temp;
int n, z;
PC = cia;
*am33
{
int srcreg, dstreg;
- unsigned long long temp;
+ unsigned64 temp;
int n, z;
PC = cia;
*am33
{
int srcreg1, srcreg2;
- long long temp, sum;
+ signed64 temp, sum;
int c, v;
PC = cia;
*am33
{
int srcreg1, srcreg2;
- unsigned long long temp, sum;
+ unsigned64 temp, sum;
int c, v;
PC = cia;
*am33
{
int srcreg1, srcreg2;
- long temp, sum;
+ signed32 temp, sum;
int v;
PC = cia;
*am33
{
int srcreg1, srcreg2;
- long long temp, sum;
+ signed64 temp, sum;
int v;
PC = cia;
*am33
{
int srcreg1, srcreg2;
- long long temp, sum;
+ signed64 temp, sum;
int c, v;
PC = cia;
*am33
{
int srcreg1, srcreg2;
- long long temp, sum;
+ signed64 temp, sum;
int c, v;
PC = cia;
*am33
{
int srcreg1, srcreg2;
- long temp, temp2, sum;
+ signed32 temp, temp2, sum;
int v;
PC = cia;
*am33
{
int srcreg1, srcreg2;
- unsigned long temp, temp2, sum;
+ unsigned32 temp, temp2, sum;
int v;
PC = cia;
*am33
{
int srcreg, dstreg;
- long temp;
+ signed32 temp;
PC = cia;
srcreg = translate_rreg (SD_, RM2);
*am33
{
int srcreg, dstreg;
- unsigned long temp;
+ unsigned32 temp;
PC = cia;
srcreg = translate_rreg (SD_, RM2);
/* 32bit saturation. */
if (State.regs[srcreg] == 0x20)
{
- long long tmp;
+ signed64 tmp;
tmp = State.regs[REG_MCRH];
tmp <<= 32;
/* 16bit saturation */
else if (State.regs[srcreg] == 0x10)
{
- long long tmp;
+ signed64 tmp;
tmp = State.regs[REG_MCRH];
tmp <<= 32;
/* 8 bit saturation */
else if (State.regs[srcreg] == 0x8)
{
- long long tmp;
+ signed64 tmp;
tmp = State.regs[REG_MCRH];
tmp <<= 32;
/* 9 bit saturation */
else if (State.regs[srcreg] == 0x9)
{
- long long tmp;
+ signed64 tmp;
tmp = State.regs[REG_MCRH];
tmp <<= 32;
/* 9 bit saturation */
else if (State.regs[srcreg] == 0x30)
{
- long long tmp;
+ signed64 tmp;
tmp = State.regs[REG_MCRH];
tmp <<= 32;
{
int dstreg, imm;
int z, c, n, v;
- unsigned long reg1, reg2, sum;
+ unsigned32 reg1, reg2, sum;
PC = cia;
dstreg = translate_rreg (SD_, RN0);
{
int imm, dstreg;
int z, c, n, v;
- unsigned long reg1, reg2, difference;
+ unsigned32 reg1, reg2, difference;
PC = cia;
dstreg = translate_rreg (SD_, RN0);
*am33
{
int dstreg;
- long temp;
+ signed32 temp;
int c, z, n;
PC = cia;
*am33
{
int dstreg;
- unsigned long long temp;
+ unsigned64 temp;
int z, n;
PC = cia;
*am33
{
int dstreg;
- unsigned long long temp;
+ unsigned64 temp;
int z, n;
PC = cia;
*am33
{
int srcreg;
- long long temp, sum;
+ signed64 temp, sum;
int c, v;
PC = cia;
*am33
{
int srcreg;
- long long temp, sum;
+ signed64 temp, sum;
int c, v;
PC = cia;
*am33
{
int srcreg;
- long long temp, sum;
+ signed64 temp, sum;
int c, v;
PC = cia;
*am33
{
int srcreg;
- long long temp, sum;
+ signed64 temp, sum;
int c, v;
PC = cia;
*am33
{
int srcreg;
- long long temp, sum;
+ signed64 temp, sum;
int c, v;
PC = cia;
*am33
{
int srcreg;
- long long temp, sum;
+ signed64 temp, sum;
int c, v;
PC = cia;
/* 32bit saturation. */
if (IMM8 == 0x20)
{
- long long tmp;
+ signed64 tmp;
tmp = State.regs[REG_MCRH];
tmp <<= 32;
/* 16bit saturation */
else if (IMM8 == 0x10)
{
- long long tmp;
+ signed64 tmp;
tmp = State.regs[REG_MCRH];
tmp <<= 32;
/* 8 bit saturation */
else if (IMM8 == 0x8)
{
- long long tmp;
+ signed64 tmp;
tmp = State.regs[REG_MCRH];
tmp <<= 32;
/* 9 bit saturation */
else if (IMM8 == 0x9)
{
- long long tmp;
+ signed64 tmp;
tmp = State.regs[REG_MCRH];
tmp <<= 32;
/* 9 bit saturation */
else if (IMM8 == 0x30)
{
- long long tmp;
+ signed64 tmp;
tmp = State.regs[REG_MCRH];
tmp <<= 32;
*am33
{
int z, c, n, v;
- unsigned long sum, source1, source2;
+ unsigned32 sum, source1, source2;
int srcreg1, srcreg2, dstreg;
PC = cia;
*am33
{
int z, c, n, v;
- unsigned long sum, source1, source2;
+ unsigned32 sum, source1, source2;
int srcreg1, srcreg2, dstreg;
PC = cia;
*am33
{
int z, c, n, v;
- unsigned long difference, source1, source2;
+ unsigned32 difference, source1, source2;
int srcreg1, srcreg2, dstreg;
PC = cia;
*am33
{
int z, c, n, v;
- unsigned long difference, source1, source2;
+ unsigned32 difference, source1, source2;
int srcreg1, srcreg2, dstreg;
PC = cia;
*am33
{
int z, c, n;
- long temp;
+ signed32 temp;
int srcreg1, srcreg2, dstreg;
PC = cia;
*am33
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- signed long long temp;
+ signed64 temp;
int n, z;
PC = cia;
*am33
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- signed long long temp;
+ signed64 temp;
int n, z;
PC = cia;
*am33
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- signed long long temp;
- unsigned long sum;
+ signed64 temp;
+ unsigned32 sum;
int c, v;
PC = cia;
*am33
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- signed long long temp;
- unsigned long sum;
+ signed64 temp;
+ unsigned32 sum;
int c, v;
PC = cia;
*am33
{
int srcreg1, srcreg2, dstreg;
- long temp, sum;
+ signed32 temp, sum;
int v;
PC = cia;
*am33
{
int srcreg1, srcreg2, dstreg;
- long temp, sum;
+ signed32 temp, sum;
int v;
PC = cia;
*am33
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- long long temp, sum;
+ signed64 temp, sum;
int v;
PC = cia;
*am33
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- long long temp, sum;
+ signed64 temp, sum;
int v;
PC = cia;
*am33
{
int srcreg1, srcreg2, dstreg;
- long temp, temp2, sum;
+ signed32 temp, temp2, sum;
int v;
PC = cia;
*am33
{
int srcreg1, srcreg2, dstreg;
- long temp, temp2, sum;
+ signed32 temp, temp2, sum;
int v;
PC = cia;
*am33
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- signed long long temp;
+ signed64 temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM2);
*am33
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- signed long long temp;
+ signed64 temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM2);
*am33
{
int dstreg, z, n, c, v;
- unsigned long sum, imm, reg2;
+ unsigned32 sum, imm, reg2;
PC = cia;
dstreg = translate_rreg (SD_, RN0);
*am33
{
int dstreg, z, n, c, v;
- unsigned long difference, imm, reg2;
+ unsigned32 difference, imm, reg2;
PC = cia;
dstreg = translate_rreg (SD_, RN0);
*am33
{
int dstreg;
- long temp;
+ signed32 temp;
int c, z, n;
PC = cia;
*am33
{
int dstreg;
- unsigned long long temp;
+ unsigned64 temp;
int z, n;
PC = cia;
*am33
{
int dstreg;
- unsigned long long temp;
+ unsigned64 temp;
int z, n;
PC = cia;
*am33
{
int srcreg;
- long long temp, sum;
+ signed64 temp, sum;
int c, v;
PC = cia;
*am33
{
int srcreg;
- long long temp, sum;
+ signed64 temp, sum;
int c, v;
PC = cia;
*am33
{
int srcreg;
- long long temp, sum;
+ signed64 temp, sum;
int c, v;
PC = cia;
*am33
{
int srcreg;
- long long temp, sum;
+ signed64 temp, sum;
int c, v;
PC = cia;
*am33
{
int srcreg;
- long long temp, sum;
+ signed64 temp, sum;
int c, v;
PC = cia;
*am33
{
int srcreg;
- long long temp, sum;
+ signed64 temp, sum;
int c, v;
PC = cia;
*am33
{
int dstreg;
- unsigned int imm, reg2, sum;
+ unsigned32 imm, reg2, sum;
int z, n, c, v;
PC = cia;
*am33
{
int dstreg;
- unsigned int imm, reg2, difference;
+ unsigned32 imm, reg2, difference;
int z, n, c, v;
PC = cia;
*am33
{
int dstreg;
- long temp;
+ signed32 temp;
int c, z, n;
PC = cia;
*am33
{
int dstreg;
- unsigned long long temp;
+ unsigned64 temp;
int z, n;
PC = cia;
*am33
{
int dstreg;
- unsigned long long temp;
+ unsigned64 temp;
int z, n;
PC = cia;
*am33
{
int srcreg, imm;
- long long temp, sum;
+ signed64 temp, sum;
int c, v;
PC = cia;
*am33
{
int srcreg, imm;
- long long temp, sum;
+ signed64 temp, sum;
int c, v;
PC = cia;
*am33
{
int srcreg, imm;
- long temp, sum;
+ signed32 temp, sum;
int v;
PC = cia;
*am33
{
int srcreg, imm;
- long temp, sum;
+ signed32 temp, sum;
int v;
PC = cia;
*am33
{
int srcreg, imm;
- long temp, sum;
+ signed32 temp, sum;
int v;
PC = cia;
*am33
{
int srcreg, imm;
- long temp, sum;
+ signed32 temp, sum;
int v;
PC = cia;
*am33
{
int srcreg, imm;
- long temp, temp2, sum;
+ signed32 temp, temp2, sum;
int v;
PC = cia;
*am33
{
int srcreg, imm;
- long temp, temp2, sum;
+ signed32 temp, temp2, sum;
int v;
PC = cia;
*am33
{
int imm, dstreg;
- long temp;
+ signed32 temp;
PC = cia;
dstreg = translate_rreg (SD_, RN0);
*am33
{
int imm, dstreg;
- long temp;
+ signed32 temp;
PC = cia;
dstreg = translate_rreg (SD_, RN0);
*am33
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- long temp, temp2, sum;
+ signed32 temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
*am33
{
int srcreg1, dstreg1, dstreg2;
- long temp, temp2, sum;
+ signed32 temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
*am33
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- long temp, temp2, sum;
+ signed32 temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
*am33
{
int srcreg1, dstreg1, dstreg2;
- long temp, temp2, sum;
+ signed32 temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
*am33
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- long temp, temp2, sum;
+ signed32 temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
*am33
{
int srcreg1, dstreg1, dstreg2;
- long temp, temp2, sum;
+ signed32 temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
*am33
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- long temp, temp2, sum;
+ signed32 temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
*am33
{
int srcreg1, dstreg1, dstreg2;
- long temp, temp2, sum;
+ signed32 temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
*am33
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- long temp, temp2, sum;
+ signed32 temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
*am33
{
int srcreg1, dstreg1, dstreg2;
- long temp, temp2, sum;
+ signed32 temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
*am33
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- long temp, temp2, sum;
+ signed32 temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
*am33
{
int srcreg1, dstreg1, dstreg2;
- long temp, temp2, sum;
+ signed32 temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
*am33
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- long temp, temp2, sum;
+ signed32 temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
*am33
{
int srcreg1, dstreg1, dstreg2;
- long temp, temp2, sum;
+ signed32 temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
:option:::insn-specifying-widths:true
:option:::hi-bit-nr:7
:model:::mn10300:mn10300:
+:model:::am33:am33:
// What do we do with an illegal instruction?
:internal::::illegal:
4.0x8,2.DM1,2.DN0=DM1+8.IMM8:S0i:::mov
"mov"
*mn10300
+*am33
{
/* OP_8000 (); */
signed32 immed = EXTEND8 (IMM8);
4.0x8,2.DM1,2.DN0!DM1:S0:::mov
"mov"
*mn10300
+*am33
{
PC = cia;
/* OP_80 (); */
8.0xf1+1110,2.DM1,2.AN0:D0:::mov
"mov"
*mn10300
+*am33
{
/* OP_F1E0 (); */
PC = cia;
8.0xf1+1101,2.AM1,2.DN0:D0a:::mov
"mov"
*mn10300
+*am33
{
/* OP_F1D0 (); */
PC = cia;
4.0x9,2.AM1,2.AN0=AM1+8.IMM8:S0ai:::mov
"mov"
*mn10300
+*am33
{
PC = cia;
/* OP_9000 (); */
4.0x9,2.AM1,2.AN0!AM1:S0a:::mov
"mov"
*mn10300
+*am33
{
PC = cia;
/* OP_90 (); */
4.0x3,11,2.AN0:S0b:::mov
"mov"
*mn10300
+*am33
{
/* OP_3C (); */
PC = cia;
8.0xf2+4.0xf,2.AM1,00:D0b:::mov
"mov"
*mn10300
+*am33
{
/* OP_F2F0 (); */
PC = cia;
8.0xf2+4.0xe,01,2.DN0:D0c:::mov
"mov"
*mn10300
+*am33
{
/* OP_F2E4 (); */
PC = cia;
8.0xf2+4.0xf,2.DM1,11:D0d:::mov
"mov"
*mn10300
+*am33
{
/* OP_F2F3 (); */
PC = cia;
8.0xf2+4.0xe,00,2.DN0:D0e:::mov
"mov"
*mn10300
+*am33
{
/* OP_F2E0 (); */
PC = cia;
8.0xf2+4.0xf,2.DM1,10:D0f:::mov
"mov"
*mn10300
+*am33
{
/* OP_F2F2 (); */
PC = cia;
4.0x7,2.DN1,2.AM0:S0c:::mov
"mov"
*mn10300
+*am33
{
/* OP_70 (); */
PC = cia;
8.0xf8+4.0x0,2.DN1,2.AM0+8.D8:D1:::mov
"mov"
*mn10300
+*am33
{
/* OP_F80000 (); */
PC = cia;
8.0xfa+4.0x0,2.DN1,2.AM0+8.D16A+8.D16B:D2:::mov
"mov"
*mn10300
+*am33
{
/* OP_FA000000 (); */
PC = cia;
8.0xfc+4.0x0,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mov
"mov"
*mn10300
+*am33
{
/* OP_FC000000 (); */
PC = cia;
4.0x5,10,2.DN0+8.D8:S1:::mov
"mov"
*mn10300
+*am33
{
/* OP_5800 (); */
PC = cia;
8.0xfa+4.0xb,01,2.DN0+8.IMM16A+8.IMM16B:D2a:::mov
"mov"
*mn10300
+*am33
{
/* OP_FAB40000 (); */
PC = cia;
8.0xfc+4.0xb,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::mov
"mov"
*mn10300
+*am33
{
/* OP_FCB40000 (); */
PC = cia;
8.0xf3+00,2.DN2,2.DI,2.AM0:D0g:::mov
"mov"
*mn10300
+*am33
{
/* OP_F300 (); */
PC = cia;
4.0x3,00,2.DN0+8.IMM16A+8.IMM16B:S2:::mov
"mov"
*mn10300
+*am33
{
/* OP_300000 (); */
PC = cia;
8.0xfc+4.0xa,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::mov
"mov"
*mn10300
+*am33
{
/* OP_FCA40000 (); */
PC = cia;
8.0xf0+4.0x0,2.AN1,2.AM0:D0h:::mov
"mov"
*mn10300
+*am33
{
/* OP_F000 (); */
PC = cia;
8.0xf8+4.0x2,2.AN1,2.AM0+8.D8:D1a:::mov
"mov"
*mn10300
+*am33
{
/* OP_F82000 (); */
PC = cia;
8.0xfa+4.0x2,2.AN1,2.AM0+8.D16A+8.D16B:D2b:::mov
"mov"
*mn10300
+*am33
{
/* OP_FA200000 (); */
PC = cia;
8.0xfc+4.0x2,2.AN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::mov
"mov"
*mn10300
+*am33
{
/* OP_FC200000 (); */
PC = cia;
4.0x5,11,2.AN0+8.D8:S1a:::mov
"mov"
*mn10300
+*am33
{
/* OP_5C00 (); */
PC = cia;
8.0xfa+4.0xb,00,2.AN0+8.IMM16A+8.IMM16B:D2c:::mov
"mov"
*mn10300
+*am33
{
/* OP_FAB00000 (); */
PC = cia;
8.0xfc+4.0xb,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::mov
"mov"
*mn10300
+*am33
{
/* OP_FCB00000 (); */
PC = cia;
8.0xf3+10,2.AN2,2.DI,2.AM0:D0i:::mov
"mov"
*mn10300
+*am33
{
/* OP_F380 (); */
PC = cia;
8.0xfa+4.0xa,00,2.AN0+8.IMM16A+8.IMM16B:D2d:::mov
"mov"
*mn10300
+*am33
{
/* OP_FAA00000 (); */
PC = cia;
8.0xfc+4.0xa,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::mov
"mov"
*mn10300
+*am33
{
/* OP_FCA00000 (); */
PC = cia;
8.0xf8+4.0xf,00,2.AM0+8.D8:D1b:::mov
"mov"
*mn10300
+*am33
{
/* OP_F8F000 (); */
PC = cia;
4.0x6,2.DM1,2.AN0:S0d:::mov
"mov"
*mn10300
+*am33
{
/* OP_60 (); */
PC = cia;
8.0xf8+4.0x1,2.DM1,2.AN0+8.D8:D1c:::mov
"mov"
*mn10300
+*am33
{
/* OP_F81000 (); */
PC = cia;
8.0xfa+4.0x1,2.DM1,2.AN0+8.D16A+8.D16B:D2e:::mov
"mov"
*mn10300
+*am33
{
/* OP_FA100000 (); */
PC = cia;
8.0xfc+4.0x1,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4f:::mov
"mov"
*mn10300
+*am33
{
/* OP_FC100000 (); */
PC = cia;
4.0x4,2.DM1,10+8.D8:S1b:::mov
"mov"
*mn10300
+*am33
{
/* OP_4200 (); */
PC = cia;
8.0xfa+4.0x9,2.DM1,01+8.IMM16A+8.IMM16B:D2f:::mov
"mov"
*mn10300
+*am33
{
/* OP_FA910000 (); */
PC = cia;
8.0xfc+4.0x9,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4g:::mov
"mov"
*mn10300
+*am33
{
/* OP_FC910000 (); */
PC = cia;
8.0xf3+01,2.DM2,2.DI,2.AN0:D0j:::mov
"mov"
*mn10300
+*am33
{
/* OP_F340 (); */
PC = cia;
4.0x0,2.DM1,01+8.IMM16A+8.IMM16B:S2a:::mov
"mov"
*mn10300
+*am33
{
/* OP_10000 (); */
PC = cia;
8.0xfc+4.0x8,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4h:::mov
"mov"
*mn10300
+*am33
{
/* OP_FC810000 (); */
PC = cia;
8.0xf0+4.0x1,2.AM1,2.AN0:D0k:::mov
"mov"
*mn10300
+*am33
{
/* OP_F010 (); */
PC = cia;
8.0xf8+4.0x3,2.AM1,2.AN0+8.D8:D1d:::mov
"mov"
*mn10300
+*am33
{
/* OP_F83000 (); */
PC = cia;
8.0xfa+4.0x3,2.AM1,2.AN0+8.D16A+8.D16B:D2g:::mov
"mov"
*mn10300
+*am33
{
/* OP_FA300000 (); */
PC = cia;
8.0xfc+4.0x3,2.AM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4i:::mov
"mov"
*mn10300
+*am33
{
/* OP_FC300000 (); */
PC = cia;
4.0x4,2.AM1,11+8.D8:S1c:::mov
"mov"
*mn10300
+
+*am33
+
{
/* OP_4300 (); */
PC = cia;
8.0xfa+4.0x9,2.AM1,00+8.IMM16A+8.IMM16B:D2h:::mov
"mov"
*mn10300
+
+*am33
+
{
/* OP_FA900000 (); */
PC = cia;
8.0xfc+4.0x9,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4j:::mov
"mov"
*mn10300
+
+*am33
+
{
/* OP_FC900000 (); */
PC = cia;
8.0xf3+11,2.AM2,2.DI,2.AN0:D0l:::mov
"mov"
*mn10300
+
+*am33
+
{
/* OP_F3C0 (); */
PC = cia;
8.0xfa+4.0x8,2.AM1,00+8.IMM16A+8.IMM16B:D2i:::mov
"mov"
*mn10300
+
+*am33
+
{
/* OP_FA800000 (); */
PC = cia;
8.0xfc+4.0x8,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4k:::mov
"mov"
*mn10300
+
+*am33
+
{
/* OP_FC800000 (); */
PC = cia;
8.0xf8+4.0xf,01,2.AN0+8.D8:D1e:::mov
"mov"
*mn10300
+
+*am33
+
{
/* OP_F8F400 (); */
PC = cia;
4.0x2,11,2.DN0+8.IMM16A+8.IMM16B:S2b:::mov
"mov"
*mn10300
+
+*am33
+
{
/* OP_2C0000 (); */
- unsigned long value;
+ unsigned32 value;
PC = cia;
value = EXTEND16 (FETCH16(IMM16A, IMM16B));
8.0xfc+4.0xc,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4l:::mov
"mov"
*mn10300
+
+*am33
+
{
/* OP_FCCC0000 (); */
- unsigned long value;
+ unsigned32 value;
PC = cia;
value = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
4.0x2,01,2.AN0+8.IMM16A+8.IMM16B:S2c:::mov
"mov"
*mn10300
+
+*am33
+
{
/* OP_240000 (); */
- unsigned long value;
+ unsigned32 value;
PC = cia;
value = FETCH16(IMM16A, IMM16B);
8.0xfc+4.0xd,11,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4m:::mov
"mov"
*mn10300
+
+*am33
+
{
/* OP_FCDC0000 (); */
PC = cia;
8.0xf0+4.0x4,2.DN1,2.AM0:D0:::movbu
"movbu"
*mn10300
+
+*am33
+
{
/* OP_F040 (); */
PC = cia;
8.0xf8+4.0x4,2.DN1,2.AM0+8.D8:D1f:::movbu
"movbu"
*mn10300
+
+*am33
+
{
/* OP_F84000 (); */
PC = cia;
8.0xfa+4.0x4,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movbu
"movbu"
*mn10300
+
+*am33
+
{
/* OP_FA400000 (); */
PC = cia;
8.0xfc+4.0x4,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movbu
"movbu"
*mn10300
+
+*am33
+
{
/* OP_FC400000 (); */
PC = cia;
8.0xf8+4.0xb,10,2.DN0+8.D8:D1a:::movbu
"movbu"
*mn10300
+
+*am33
+
{
/* OP_F8B800 (); */
PC = cia;
8.0xfa+4.0xb,10,2.DN0+8.IMM16A+8.IMM16B:D2a:::movbu
"movbu"
*mn10300
+
+*am33
+
{
/* OP_FAB80000 (); */
PC = cia;
8.0xfc+4.0xb,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movbu
"movbu"
*mn10300
+
+*am33
+
{
/* OP_FCB80000 (); */
PC = cia;
8.0xf4+00,2.DN2,2.DI,2.AM0:D0a:::movbu
"movbu"
*mn10300
+
+*am33
+
{
/* OP_F400 (); */
PC = cia;
4.0x3,01,2.DN0+8.IMM16A+8.IMM16B:S2:::movbu
"movbu"
*mn10300
+
+*am33
+
{
/* OP_340000 (); */
PC = cia;
8.0xfc+4.0xa,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movbu
"movbu"
*mn10300
+
+*am33
+
{
/* OP_FCA80000 (); */
PC = cia;
8.0xf0+4.0x5,2.DM1,2.AN0:D0b:::movbu
"movbu"
*mn10300
+
+*am33
+
{
/* OP_F050 (); */
PC = cia;
8.0xf8+4.0x5,2.DM1,2.AN0+8.D8:D1b:::movbu
"movbu"
*mn10300
+
+*am33
+
{
/* OP_F85000 (); */
PC = cia;
8.0xfa+4.0x5,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movbu
"movbu"
*mn10300
+
+*am33
+
{
/* OP_FA500000 (); */
PC = cia;
8.0xfc+4.0x5,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movbu
"movbu"
*mn10300
+
+*am33
+
{
/* OP_FC500000 (); */
PC = cia;
8.0xf8+4.0x9,2.DM1,10+8.D8:D1c:::movbu
"movbu"
*mn10300
+
+*am33
+
{
/* OP_F89200 (); */
PC = cia;
8.0xfa+4.0x9,2.DM1,10+8.IMM16A+8.IMM16B:D2c:::movbu
"movbu"
*mn10300
+
+*am33
+
{
/* OP_FA920000 (); */
PC = cia;
8.0xfc+4.0x9,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movbu
"movbu"
*mn10300
+
+*am33
+
{
/* OP_FC920000 (); */
PC = cia;
8.0xf4+01,2.DM2,2.DI,2.AN0:D0c:::movbu
"movbu"
*mn10300
+
+*am33
+
{
/* OP_F440 (); */
PC = cia;
4.0x0,2.DM1,10+8.IMM16A+8.IMM16B:S2a:::movbu
"movbu"
*mn10300
+
+*am33
+
{
/* OP_20000 (); */
PC = cia;
8.0xfc+4.0x8,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movbu
"movbu"
*mn10300
+
+*am33
+
{
/* OP_FC820000 (); */
PC = cia;
8.0xf0+4.0x6,2.DN1,2.AM0:D0:::movhu
"movhu"
*mn10300
+
+*am33
+
{
/* OP_F060 (); */
PC = cia;
8.0xf8+4.0x6,2.DN1,2.AM0+8.D8:D1d:::movhu
"movhu"
*mn10300
+
+*am33
+
{
/* OP_F86000 (); */
PC = cia;
8.0xfa+4.0x6,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movhu
"movhu"
*mn10300
+
+*am33
+
{
/* OP_FA600000 (); */
PC = cia;
8.0xfc+4.0x6,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movhu
"movhu"
*mn10300
+
+*am33
+
{
/* OP_FC600000 (); */
PC = cia;
8.0xf8+4.0xb,11,2.DN0+8.D8:D1a:::movhu
"movhu"
*mn10300
+
+*am33
+
{
/* OP_F8BC00 (); */
PC = cia;
8.0xfa+4.0xb,11,2.DN0+8.IMM16A+8.IMM16B:D2a:::movhu
"movhu"
*mn10300
+
+*am33
+
{
/* OP_FABC0000 (); */
PC = cia;
8.0xfc+4.0xb,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movhu
"movhu"
*mn10300
+
+*am33
+
{
/* OP_FCBC0000 (); */
PC = cia;
8.0xf4+10,2.DN2,2.DI,2.AM0:D0a:::movhu
"movhu"
*mn10300
+
+*am33
+
{
/* OP_F480 (); */
PC = cia;
4.0x3,10,2.DN0+8.IMM16A+8.IMM16B:S2:::movhu
"movhu"
*mn10300
+
+*am33
+
{
/* OP_380000 (); */
PC = cia;
8.0xfc+4.0xa,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movhu
"movhu"
*mn10300
+
+*am33
+
{
/* OP_FCAC0000 (); */
PC = cia;
8.0xf0+4.0x7,2.DM1,2.AN0:D0b:::movhu
"movhu"
*mn10300
+
+*am33
+
{
/* OP_F070 (); */
PC = cia;
8.0xf8+4.0x7,2.DM1,2.AN0+8.D8:D1b:::movhu
"movhu"
*mn10300
+
+*am33
+
{
/* OP_F87000 (); */
PC = cia;
8.0xfa+4.0x7,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movhu
"movhu"
*mn10300
+
+*am33
+
{
/* OP_FA700000 (); */
PC = cia;
8.0xfc+4.0x7,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movhu
"movhu"
*mn10300
+
+*am33
+
{
/* OP_FC700000 (); */
PC = cia;
8.0xf8+4.0x9,2.DM1,11+8.D8:D1c:::movhu
"movhu"
*mn10300
+
+*am33
+
{
/* OP_F89300 (); */
PC = cia;
8.0xfa+4.0x9,2.DM1,11+8.IMM16A+8.IMM16B:D2c:::movhu
"movhu"
*mn10300
+
+*am33
+
{
/* OP_FA930000 (); */
PC = cia;
8.0xfc+4.0x9,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movhu
"movhu"
*mn10300
+
+*am33
+
{
/* OP_FC930000 (); */
PC = cia;
8.0xf4+11,2.DM2,2.DI,2.AN0:D0c:::movhu
"movhu"
*mn10300
+
+*am33
+
{
/* OP_F4C0 (); */
PC = cia;
4.0x0,2.DM1,11+8.IMM16A+8.IMM16B:S2a:::movhu
"movhu"
*mn10300
+
+*am33
+
{
/* OP_30000 (); */
PC = cia;
8.0xfc+4.0x8,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movhu
"movhu"
*mn10300
+
+*am33
+
{
/* OP_FC830000 (); */
PC = cia;
8.0xf2+4.0xd,00,2.DN0:D0:::ext
"ext"
*mn10300
+
+*am33
+
{
/* OP_F2D0 (); */
PC = cia;
4.0x1,00,2.DN0:S0:::extb
"extb"
*mn10300
+
+*am33
+
{
/* OP_10 (); */
PC = cia;
4.0x1,01,2.DN0:S0:::extbu
"extbu"
*mn10300
+
+*am33
+
{
/* OP_14 (); */
PC = cia;
4.0x1,10,2.DN0:S0:::exth
"exth"
*mn10300
+
+*am33
+
{
/* OP_18 (); */
PC = cia;
4.0x1,11,2.DN0:S0:::exthu
"exthu"
*mn10300
+
+*am33
+
{
/* OP_1C (); */
PC = cia;
4.0x0,2.DN1,00:S0:::clr
"clr"
*mn10300
+
+*am33
+
{
/* OP_0 (); */
PC = cia;
4.0xe,2.DM1,2.DN0:S0:::add
"add"
*mn10300
+
+*am33
+
{
/* OP_E0 (); */
PC = cia;
8.0xf1+4.0x6,2.DM1,2.AN0:D0:::add
"add"
*mn10300
+
+*am33
+
{
/* OP_F160 (); */
PC = cia;
8.0xf1+4.0x5,2.AM1,2.DN0:D0a:::add
"add"
*mn10300
+
+*am33
+
{
/* OP_F150 (); */
PC = cia;
8.0xf1+4.0x7,2.AM1,2.AN0:D0b:::add
"add"
*mn10300
+
+*am33
+
{
/* OP_F170 (); */
PC = cia;
4.0x2,10,2.DN0+8.IMM8:S1:::add
"add"
*mn10300
+
+*am33
+
{
/* OP_2800 (); */
PC = cia;
8.0xfa+4.0xc,00,2.DN0+8.IMM16A+8.IMM16B:D2:::add
"add"
*mn10300
+
+*am33
+
{
/* OP_FAC00000 (); */
PC = cia;
8.0xfc+4.0xc,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::add
"add"
*mn10300
+
+*am33
+
{
/* OP_FCC00000 (); */
PC = cia;
4.0x2,00,2.AN0+8.IMM8:S1a:::add
"add"
*mn10300
+
+*am33
+
{
/* OP_2000 (); */
PC = cia;
8.0xfa+4.0xd,00,2.AN0+8.IMM16A+8.IMM16B:D2a:::add
"add"
*mn10300
+
+*am33
+
{
/* OP_FAD00000 (); */
PC = cia;
8.0xfc+4.0xd,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::add
"add"
*mn10300
+
+*am33
+
{
/* OP_FCD00000 (); */
PC = cia;
8.0xf8+8.0xfe+8.IMM8:D1:::add
"add"
*mn10300
+
+*am33
+
{
/* OP_F8FE00 (); */
- unsigned long imm;
+ unsigned32 imm;
/* Note: no PSW changes. */
PC = cia;
8.0xfa+8.0xfe+8.IMM16A+8.IMM16B:D2b:::add
"add"
*mn10300
+
+*am33
+
{
/* OP_FAFE0000 (); */
- unsigned long imm;
+ unsigned32 imm;
/* Note: no PSW changes. */
PC = cia;
8.0xfc+8.0xfe+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::add
"add"
*mn10300
+
+*am33
+
{
/* OP_FCFE0000 (); */
- unsigned long imm;
+ unsigned32 imm;
/* Note: no PSW changes. */
PC = cia;
8.0xf1+4.0x4,2.DM1,2.DN0:D0:::addc
"addc"
*mn10300
+
+*am33
+
{
/* OP_F140 (); */
int z, c, n, v;
- unsigned long reg1, reg2, sum;
+ unsigned32 reg1, reg2, sum;
PC = cia;
reg1 = State.regs[REG_D0 + DM1];
8.0xf1+4.0x0,2.DM1,2.DN0:D0:::sub
"sub"
*mn10300
+
+*am33
+
{
/* OP_F100 (); */
PC = cia;
8.0xf1+4.0x2,2.DM1,2.AN0:D0a:::sub
"sub"
*mn10300
+
+*am33
+
{
/* OP_F120 (); */
PC = cia;
8.0xf1+4.0x1,2.AM1,2.DN0:D0b:::sub
"sub"
*mn10300
+
+*am33
+
{
/* OP_F110 (); */
PC = cia;
8.0xf1+4.0x3,2.AM1,2.AN0:D0c:::sub
"sub"
*mn10300
+
+*am33
+
{
/* OP_F130 (); */
PC = cia;
8.0xfc+4.0xc,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::sub
"sub"
*mn10300
+
+*am33
+
{
/* OP_FCC40000 (); */
PC = cia;
8.0xfc+4.0xd,01,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::sub
"sub"
*mn10300
+
+*am33
+
{
/* OP_FCD40000 (); */
PC = cia;
8.0xf1+4.0x8,2.DM1,2.DN0:D0:::subc
"subc"
*mn10300
+
+*am33
+
{
/* OP_F180 (); */
int z, c, n, v;
- unsigned long reg1, reg2, difference;
+ unsigned32 reg1, reg2, difference;
PC = cia;
reg1 = State.regs[REG_D0 + DM1];
8.0xf2+4.0x4,2.DM1,2.DN0:D0:::mul
"mul"
*mn10300
+
+*am33
+
{
/* OP_F240 (); */
- unsigned long long temp;
+ unsigned64 temp;
int n, z;
PC = cia;
8.0xf2+4.0x5,2.DM1,2.DN0:D0:::mulu
"mulu"
*mn10300
+
+*am33
+
{
/* OP_F250 (); */
- unsigned long long temp;
+ unsigned64 temp;
int n, z;
PC = cia;
8.0xf2+4.0x6,2.DM1,2.DN0:D0:::div
"div"
*mn10300
+
+*am33
+
{
/* OP_F260 (); */
signed64 temp;
8.0xf2+4.0x7,2.DM1,2.DN0:D0:::divu
"divu"
*mn10300
+
+*am33
+
{
/* OP_F270 (); */
unsigned64 temp;
4.0x4,2.DN1,00:S0:::inc
"inc"
*mn10300
+
+*am33
+
{
/* OP_40 (); */
- unsigned int imm;
+ unsigned32 imm;
PC = cia;
imm = 1;
4.0x4,2.AN1,01:S0a:::inc
"inc"
*mn10300
+
+*am33
+
{
/* OP_41 (); */
PC = cia;
4.0x5,00,2.AN0:S0:::inc4
"inc4"
*mn10300
+
+*am33
+
{
/* OP_50 (); */
PC = cia;
4.0xa,2.DM1,2.DN0=DM1+IMM8:S0i:::cmp
"cmp"
*mn10300
+
+*am33
+
{
PC = cia;
/* OP_A000 (); */
4.0xa,2.DM1,2.DN0!DM1:S0:::cmp
"cmp"
*mn10300
+
+*am33
+
{
PC = cia;
/* OP_A0 (); */
8.0xf1+4.0xa,2.DM1,2.AN0:D0:::cmp
"cmp"
*mn10300
+
+*am33
+
{
/* OP_F1A0 (); */
PC = cia;
8.0xf1+4.0x9,2.AM1,2.DN0:D0a:::cmp
"cmp"
*mn10300
+
+*am33
+
{
/* OP_F190 (); */
PC = cia;
4.0xb,2.AM1,2.AN0=AM1+IMM8:S0ai:::cmp
"cmp"
*mn10300
+
+*am33
+
{
PC = cia;
/* OP_B000 (); */
4.0xb,2.AM1,2.AN0!AM1:S0a:::cmp
"cmp"
*mn10300
+
+*am33
+
{
PC = cia;
/* OP_B0 (); */
8.0xfa+4.0xc,10,2.DN0+8.IMM16A+8.IMM16B:D2:::cmp
"cmp"
*mn10300
+
+*am33
+
{
/* OP_FAC80000 (); */
PC = cia;
8.0xfc+4.0xc,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::cmp
"cmp"
*mn10300
+
+*am33
+
{
/* OP_FCC80000 (); */
PC = cia;
8.0xfa+4.0xd,10,2.AN0+8.IMM16A+8.IMM16B:D2a:::cmp
"cmp"
*mn10300
+
+*am33
+
{
/* OP_FAD80000 (); */
PC = cia;
8.0xfc+4.0xd,10,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::cmp
"cmp"
*mn10300
+
+*am33
+
{
/* OP_FCD80000 (); */
PC = cia;
8.0xf2+4.0x0,2.DM1,2.DN0:D0:::and
"and"
*mn10300
+
+*am33
+
{
/* OP_F200 (); */
int n, z;
8.0xf8+4.0xe,00,2.DN0+8.IMM8:D1:::and
"and"
*mn10300
+
+*am33
+
{
/* OP_F8E000 (); */
int n, z;
8.0xfa+4.0xe,00,2.DN0+8.IMM16A+8.IMM16B:D2:::and
"and"
*mn10300
+
+*am33
+
{
/* OP_FAE00000 (); */
int n, z;
8.0xfc+4.0xe,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::and
"and"
*mn10300
+
+*am33
+
{
/* OP_FCE00000 (); */
int n, z;
8.0xfa+8.0xfc+8.IMM16A+8.IMM16B:D2a:::and
"and"
*mn10300
+
+*am33
+
{
/* OP_FAFC0000 (); */
PC = cia;
8.0xf2+4.0x1,2.DM1,2.DN0:D0:::or
"or"
*mn10300
+
+*am33
+
{
/* OP_F210 (); */
PC = cia;
8.0xf8+4.0xe,01,2.DN0+8.IMM8:D1:::or
"or"
*mn10300
+
+*am33
+
{
/* OP_F8E400 (); */
PC = cia;
8.0xfa+4.0xe,01,2.DN0+8.IMM16A+8.IMM16B:D2:::or
"or"
*mn10300
+
+*am33
+
{
/* OP_FAE40000 (); */
PC = cia;
8.0xfc+4.0xe,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::or
"or"
*mn10300
+
+*am33
+
{
/* OP_FCE40000 (); */
PC = cia;
8.0xfa+8.0xfd+8.IMM16A+8.IMM16B:D2a:::or
"or"
*mn10300
+
+*am33
+
{
/* OP_FAFD0000 (); */
PC = cia;
8.0xf2+4.0x2,2.DM1,2.DN0:D0:::xor
"xor"
*mn10300
+
+*am33
+
{
/* OP_F220 (); */
PC = cia;
8.0xfa+4.0xe,10,2.DN0+8.IMM16A+8.IMM16B:D2:::xor
"xor"
*mn10300
+
+*am33
+
{
/* OP_FAE80000 (); */
PC = cia;
8.0xfc+4.0xe,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::xor
"xor"
*mn10300
+
+*am33
+
{
/* OP_FCE80000 (); */
PC = cia;
8.0xf2+4.0x3,00,2.DN0:D0:::not
"not"
*mn10300
+
+*am33
+
{
/* OP_F230 (); */
int n, z;
8.0xf8+4.0xe,11,2.DN0+8.IMM8:D1:::btst
"btst"
*mn10300
+
+*am33
+
{
/* OP_F8EC00 (); */
PC = cia;
8.0xfa+4.0xe,11,2.DN0+8.IMM16A+8.IMM16B:D2:::btst
"btst"
*mn10300
+
+*am33
+
{
/* OP_FAEC0000 (); */
PC = cia;
8.0xfc+4.0xe,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::btst
"btst"
*mn10300
+
+*am33
+
{
/* OP_FCEC0000 (); */
PC = cia;
8.0xfe+8.0x02+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::btst
"btst"
*mn10300
+
+*am33
+
{
/* OP_FE020000 (); */
PC = cia;
8.0xfa+4.0xf,10,2.AN0+8.D8+8.IMM8:D2a:::btst
"btst"
*mn10300
+
+*am33
+
{
/* OP_FAF80000 (); */
PC = cia;
8.0xf0+4.8,2.DM1,2.AN0:D0:::bset
"bset"
*mn10300
+
+*am33
+
{
/* OP_F080 (); */
- unsigned long temp;
+ unsigned32 temp;
int z;
PC = cia;
8.0xfe+8.0x00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bset
"bset"
*mn10300
+
+*am33
+
{
/* OP_FE000000 (); */
- unsigned long temp;
+ unsigned32 temp;
int z;
PC = cia;
8.0xfa+4.0xf,00,2.AN0+8.D8+8.IMM8:D2:::bset
"bset"
*mn10300
+
+*am33
+
{
/* OP_FAF00000 (); */
- unsigned long temp;
+ unsigned32 temp;
int z;
PC = cia;
8.0xf0+4.0x9,2.DM1,2.AN0:D0:::bclr
"bclr"
*mn10300
+
+*am33
+
{
/* OP_F090 (); */
- unsigned long temp;
+ unsigned32 temp;
int z;
PC = cia;
8.0xfe+8.0x01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bclr
"bclr"
*mn10300
+
+*am33
+
{
/* OP_FE010000 (); */
- unsigned long temp;
+ unsigned32 temp;
int z;
PC = cia;
8.0xfa+4.0xf,01,2.AN0+8.D8+8.IMM8:D2:::bclr
"bclr"
*mn10300
+
+*am33
+
{
/* OP_FAF40000 (); */
- unsigned long temp;
+ unsigned32 temp;
int z;
PC = cia;
8.0xf2+4.0xb,2.DM1,2.DN0:D0:::asr
"asr"
*mn10300
+
+*am33
+
{
/* OP_F2B0 (); */
- long temp;
+ signed32 temp;
int z, n, c;
PC = cia;
8.0xf8+4.0xc,10,2.DN0+8.IMM8:D1:::asr
"asr"
*mn10300
+
+*am33
+
{
/* OP_F8C800 (); */
- long temp;
+ signed32 temp;
int z, n, c;
PC = cia;
8.0xf2+4.0xa,2.DM1,2.DN0:D0:::lsr
"lsr"
*mn10300
+
+*am33
+
{
/* OP_F2A0 (); */
int z, n, c;
8.0xf8+4.0xc,01,2.DN0+8.IMM8:D1:::lsr
"lsr"
*mn10300
+
+*am33
+
{
/* OP_F8C400 (); */
int z, n, c;
8.0xf2+4.0x9,2.DM1,2.DN0:D0:::asl
"asl"
*mn10300
+
+*am33
+
{
/* OP_F290 (); */
int n, z;
8.0xf8+4.0xc,00,2.DN0+8.IMM8:D1:::asl
"asl"
*mn10300
+
+*am33
+
{
/* OP_F8C000 (); */
int n, z;
4.0x5,01,2.DN0:S0:::asl2
"asl2"
*mn10300
+
+*am33
+
{
/* OP_54 (); */
int n, z;
8.0xf2+4.0x8,01,2.DN0:D0:::ror
"ror"
*mn10300
+
+*am33
+
{
/* OP_F284 (); */
- unsigned long value;
+ unsigned32 value;
int c,n,z;
PC = cia;
8.0xf2+4.0x8,00,2.DN0:D0:::rol
"rol"
*mn10300
+
+*am33
+
{
/* OP_F280 (); */
- unsigned long value;
+ unsigned32 value;
int c,n,z;
PC = cia;
8.0xc8+8.D8:S1:::beq
"beq"
*mn10300
+
+*am33
+
{
/* OP_C800 (); */
PC = cia;
8.0xc9+8.D8:S1:::bne
"bne"
*mn10300
+
+*am33
+
{
/* OP_C900 (); */
PC = cia;
8.0xc1+8.D8:S1:::bgt
"bgt"
*mn10300
+
+*am33
+
{
/* OP_C100 (); */
PC = cia;
8.0xc2+8.D8:S1:::bge
"bge"
*mn10300
+
+*am33
+
{
/* OP_C200 (); */
PC = cia;
8.0xc3+8.D8:S1:::ble
"ble"
*mn10300
+
+*am33
+
{
/* OP_C300 (); */
PC = cia;
8.0xc0+8.D8:S1:::blt
"blt"
*mn10300
+
+*am33
+
{
/* OP_C000 (); */
PC = cia;
8.0xc5+8.D8:S1:::bhi
"bhi"
*mn10300
+
+*am33
+
{
/* OP_C500 (); */
PC = cia;
8.0xc6+8.D8:S1:::bcc
"bcc"
*mn10300
+
+*am33
+
{
/* OP_C600 (); */
PC = cia;
8.0xc7+8.D8:S1:::bls
"bls"
*mn10300
+
+*am33
+
{
/* OP_C700 (); */
PC = cia;
8.0xc4+8.D8:S1:::bcs
"bcs"
*mn10300
+
+*am33
+
{
/* OP_C400 (); */
PC = cia;
8.0xf8+8.0xe8+8.D8:D1:::bvc
"bvc"
*mn10300
+
+*am33
+
{
/* OP_F8E800 (); */
PC = cia;
8.0xf8+8.0xe9+8.D8:D1:::bvs
"bvs"
*mn10300
+
+*am33
+
{
/* OP_F8E900 (); */
PC = cia;
8.0xf8+8.0xea+8.D8:D1:::bnc
"bnc"
*mn10300
+
+*am33
+
{
/* OP_F8EA00 (); */
PC = cia;
8.0xf8+8.0xeb+8.D8:D1:::bns
"bns"
*mn10300
+
+*am33
+
{
/* OP_F8EB00 (); */
PC = cia;
8.0xca+8.D8:S1:::bra
"bra"
*mn10300
+
+*am33
+
{
/* OP_CA00 (); */
PC = cia;
8.0xd8:S0:::leq
"leq"
*mn10300
+
+*am33
+
{
/* OP_D8 (); */
PC = cia;
8.0xd9:S0:::lne
"lne"
*mn10300
+
+*am33
+
{
/* OP_D9 (); */
PC = cia;
8.0xd1:S0:::lgt
"lgt"
*mn10300
+
+*am33
+
{
/* OP_D1 (); */
PC = cia;
8.0xd2:S0:::lge
"lge"
*mn10300
+
+*am33
+
{
/* OP_D2 (); */
PC = cia;
8.0xd3:S0:::lle
"lle"
*mn10300
+
+*am33
+
{
/* OP_D3 (); */
PC = cia;
8.0xd0:S0:::llt
"llt"
*mn10300
+
+*am33
+
{
/* OP_D0 (); */
PC = cia;
8.0xd5:S0:::lhi
"lhi"
*mn10300
+
+*am33
+
{
/* OP_D5 (); */
PC = cia;
8.0xd6:S0:::lcc
"lcc"
*mn10300
+
+*am33
+
{
/* OP_D6 (); */
PC = cia;
8.0xd7:S0:::lls
"lls"
*mn10300
+
+*am33
+
{
/* OP_D7 (); */
PC = cia;
8.0xd4:S0:::lcs
"lcs"
*mn10300
+
+*am33
+
{
/* OP_D4 (); */
PC = cia;
8.0xda:S0:::lra
"lra"
*mn10300
+
+*am33
+
{
/* OP_DA (); */
PC = cia;
8.0xdb:S0:::setlb
"setlb"
*mn10300
+
+*am33
+
{
/* OP_DB (); */
PC = cia;
8.0xf0+4.0xf,01,2.AN0:D0:::jmp
"jmp"
*mn10300
+
+*am33
+
{
/* OP_F0F4 (); */
PC = State.regs[REG_A0 + AN0];
8.0xcc+8.D16A+8.D16B:S2:::jmp
"jmp"
*mn10300
+
+*am33
+
{
/* OP_CC0000 (); */
PC = cia + EXTEND16(FETCH16(D16A, D16B));
8.0xdc+8.D32A+8.D32B+8.D32C+8.D32D:S4:::jmp
"jmp"
*mn10300
+
+*am33
+
{
/* OP_DC000000 (); */
PC = cia + FETCH32(D32A, D32B, D32C, D32D);
8.0xf0+4.0xf,00,2.AN0:D0:::calls
"calls"
*mn10300
+
+*am33
+
{
/* OP_F0F0 (); */
- unsigned int next_pc, sp;
+ unsigned32 next_pc, sp;
PC = cia;
sp = State.regs[REG_SP];
8.0xfa+8.0xff+8.D16A+8.D16B:D2:::calls
"calls"
*mn10300
+
+*am33
+
{
/* OP_FAFF0000 (); */
- unsigned int next_pc, sp;
+ unsigned32 next_pc, sp;
PC = cia;
sp = State.regs[REG_SP];
8.0xfc+8.0xff+8.D32A+8.D32B+8.D32C+8.D32D:D4:::calls
"calls"
*mn10300
+
+*am33
+
{
/* OP_FCFF0000 (); */
- unsigned int next_pc, sp;
+ unsigned32 next_pc, sp;
PC = cia;
sp = State.regs[REG_SP];
8.0xf0+8.0xfc:D0:::rets
"rets"
*mn10300
+
+*am33
+
{
/* OP_F0FC (); */
- unsigned int sp;
+ unsigned32 sp;
sp = State.regs[REG_SP];
State.regs[REG_PC] = load_word(sp);
8.0xf0+8.0xfd:D0:::rti
"rti"
*mn10300
+
+*am33
+
{
/* OP_F0FD (); */
- unsigned int sp;
+ unsigned32 sp;
sp = State.regs[REG_SP];
PSW = load_half(sp);
8.0xf0+8.0xfe:D0:::trap
"trap"
*mn10300
+
+*am33
+
{
/* OP_F0FE (); */
- unsigned int sp, next_pc;
+ unsigned32 sp, next_pc;
PC = cia;
sp = State.regs[REG_SP];
8.0xf0+8.0xff:D0:::rtm
"rtm"
*mn10300
+
+*am33
+
{
/* OP_F0FF (); */
PC = cia;
8.0xcb:S0:::nop
"nop"
*mn10300
+
+*am33
+
{
/* OP_CB (); */
PC = cia;
8.0xf6+4.0xf,2.DM1,2.DN0:D0:::getx
"getx"
*mn10300
+
+*am33
+
{
/* OP_F6F0 (); */
int z, n;
8.0xf6+4.0x0,2.DM1,2.DN0:D0:::mulq
"mulq"
*mn10300
+
+*am33
+
{
/* OP_F600 (); */
- unsigned long long temp;
+ unsigned64 temp;
int n, z;
PC = cia;
8.0xf9+4.0x,00,2.DN0+8.IMM8:D1:::mulq
"mulq"
*mn10300
+
+*am33
+
{
/* OP_F90000 (); */
- unsigned long long temp;
+ unsigned64 temp;
int n, z;
PC = cia;
8.0xfb+4.0x0,00,2.DN0+8.IMM16A+8.IMM16B:D2:::mulq
"mulq"
*mn10300
+
+*am33
+
{
/* OP_FB000000 (); */
- unsigned long long temp;
+ unsigned64 temp;
int n, z;
PC = cia;
8.0xfd+4.0x0,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulq
"mulq"
*mn10300
+
+*am33
+
{
/* OP_FD000000 (); */
- unsigned long long temp;
+ unsigned64 temp;
int n, z;
PC = cia;
8.0xf6+4.0x1,2.DM1,2.DN0:D0:::mulqu
"mulqu"
*mn10300
+
+*am33
+
{
/* OP_F610 (); */
- unsigned long long temp;
+ unsigned64 temp;
int n, z;
PC = cia;
8.0xf9+4.0x1,01,2.DN0+8.IMM8:D1:::mulqu
"mulqu"
*mn10300
+
+*am33
+
{
/* OP_F91400 (); */
- unsigned long long temp;
+ unsigned64 temp;
int n, z;
PC = cia;
8.0xfb+4.0x1,01,2.DN0+8.IMM16A+8.IMM16B:D2:::mulqu
"mulqu"
*mn10300
+
+*am33
+
{
/* OP_FB140000 (); */
- unsigned long long temp;
+ unsigned64 temp;
int n, z;
PC = cia;
8.0xfd+4.0x1,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulqu
"mulqu"
*mn10300
+
+*am33
+
{
/* OP_FD140000 (); */
- unsigned long long temp;
+ unsigned64 temp;
int n, z;
PC = cia;
8.0xf6+4.0x4,2.DM1,2.DN0:D0:::sat16
"sat16"
*mn10300
+
+*am33
+
{
/* OP_F640 (); */
int temp;
8.0xf6+4.0x5,2.DM1,2.DN0:D0:::sat24
"sat24"
*mn10300
+
+*am33
+
{
/* OP_F650 (); */
int temp;
8.0xf6+4.0x7,2.DM1,2.DN0:D0:::bsch
"bsch"
*mn10300
+
+*am33
+
{
/* OP_F670 (); */
int temp, c;
8.0xf0+8.0xc0:D0:::syscall
"syscall"
*mn10300
+
+*am33
+
{
/* OP_F0C0 (); */
PC = cia;
8.0xff:S0:::break
"break"
*mn10300
+
+*am33
+
{
/* OP_FF (); */
PC = cia;
8.0xce+8.REGS:S1:::movm
"movm"
*mn10300
+
+*am33
+
{
/* OP_CE00 (); */
- unsigned long sp = State.regs[REG_SP];
- unsigned long mask;
+ unsigned32 sp = State.regs[REG_SP];
+ unsigned32 mask;
PC = cia;
mask = REGS;
sp += 4;
}
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
+ {
+ if (mask & 0x1)
+ {
+ /* Need to restore MDQR, MCRH, MCRL, and MCVF */
+ sp += 16;
+ State.regs[REG_E0 + 1] = load_word (sp);
+ sp += 4;
+ State.regs[REG_E0 + 0] = load_word (sp);
+ sp += 4;
+ }
+
+ if (mask & 0x2)
+ {
+ State.regs[REG_E0 + 7] = load_word (sp);
+ sp += 4;
+ State.regs[REG_E0 + 6] = load_word (sp);
+ sp += 4;
+ State.regs[REG_E0 + 5] = load_word (sp);
+ sp += 4;
+ State.regs[REG_E0 + 4] = load_word (sp);
+ sp += 4;
+ }
+
+ if (mask & 0x4)
+ {
+ State.regs[REG_E0 + 3] = load_word (sp);
+ sp += 4;
+ State.regs[REG_E0 + 2] = load_word (sp);
+ sp += 4;
+ }
+ }
/* And make sure to update the stack pointer. */
State.regs[REG_SP] = sp;
8.0xcf+8.REGS:S1a:::movm
"movm"
*mn10300
+
+*am33
+
{
/* OP_CF00 (); */
- unsigned long sp = State.regs[REG_SP];
- unsigned long mask;
+ unsigned32 sp = State.regs[REG_SP];
+ unsigned32 mask;
PC = cia;
mask = REGS;
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
+ {
+ if (mask & 0x4)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 2]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 3]);
+ }
+
+ if (mask & 0x2)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 4]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 5]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 6]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 7]);
+ }
+
+ if (mask & 0x1)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 0]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 1]);
+ sp -= 16;
+ /* Need to save MDQR, MCRH, MCRL, and MCVF */
+ }
+ }
if (mask & 0x80)
{
8.0xcd+8.D16A+8.D16B+8.REGS+8.IMM8:S4:::call
"call"
*mn10300
+
+*am33
+
{
/* OP_CD000000 (); */
- unsigned int next_pc, sp;
- unsigned long mask;
+ unsigned32 next_pc, sp;
+ unsigned32 mask;
PC = cia;
sp = State.regs[REG_SP];
mask = REGS;
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
+ {
+ if (mask & 0x4)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 2]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 3]);
+ }
+
+ if (mask & 0x2)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 4]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 5]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 6]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 7]);
+ }
+
+ if (mask & 0x1)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 0]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 1]);
+ sp -= 16;
+ /* Need to save MDQR, MCRH, MCRL, and MCVF */
+ }
+ }
if (mask & 0x80)
{
8.0xdd+8.D32A+8.D32B+8.D32C+8.D32D+8.REGS+8.IMM8:S6:::call
"call"
*mn10300
+
+*am33
+
{
/* OP_DD000000 (); */
- unsigned int next_pc, sp;
- unsigned long mask;
+ unsigned32 next_pc, sp;
+ unsigned32 mask;
PC = cia;
sp = State.regs[REG_SP];
mask = REGS;
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
+ {
+ if (mask & 0x4)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 2]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 3]);
+ }
+
+ if (mask & 0x2)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 4]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 5]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 6]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 7]);
+ }
+
+ if (mask & 0x1)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 0]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 1]);
+ sp -= 16;
+ /* Need to save MDQR, MCRH, MCRL, and MCVF */
+ }
+ }
if (mask & 0x80)
{
8.0xdf+8.REGS+8.IMM8:S2:::ret
"ret"
*mn10300
+
+*am33
+
{
/* OP_DF0000 (); */
- unsigned int sp, offset;
- unsigned long mask;
+ unsigned32 sp, offset;
+ unsigned32 mask;
PC = cia;
State.regs[REG_SP] += IMM8;
offset = -4;
mask = REGS;
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
+ {
+
+ if (mask & 0x4)
+ {
+ State.regs[REG_E0 + 2] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_E0 + 3] = load_word (sp + offset);
+ offset -= 4;
+ }
+
+ if (mask & 0x2)
+ {
+ State.regs[REG_E0 + 4] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_E0 + 5] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_E0 + 6] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_E0 + 7] = load_word (sp + offset);
+ offset -= 4;
+ }
+
+ if (mask & 0x1)
+ {
+ /* Need to restore MDQR, MCRH, MCRL, and MCVF */
+ offset -= 16;
+ State.regs[REG_E0 + 0] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_E0 + 1] = load_word (sp + offset);
+ offset -= 4;
+ }
+
+ }
if (mask & 0x80)
{
8.0xde+8.REGS+8.IMM8:S2:::retf
"retf"
*mn10300
+
+*am33
+
{
/* OP_DE0000 (); */
- unsigned int sp, offset;
- unsigned long mask;
+ unsigned32 sp, offset;
+ unsigned32 mask;
PC = cia;
State.regs[REG_SP] += IMM8;
sp = State.regs[REG_SP];
- State.regs[REG_PC] = State.regs[REG_MDR] - 3;
+ State.regs[REG_PC] = State.regs[REG_MDR];
offset = -4;
mask = REGS;
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
+ {
+
+ if (mask & 0x4)
+ {
+ State.regs[REG_E0 + 2] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_E0 + 3] = load_word (sp + offset);
+ offset -= 4;
+ }
+
+ if (mask & 0x2)
+ {
+ State.regs[REG_E0 + 4] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_E0 + 5] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_E0 + 6] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_E0 + 7] = load_word (sp + offset);
+ offset -= 4;
+ }
+
+ if (mask & 0x1)
+ {
+ /* Need to restore MDQR, MCRH, MCRL, and MCVF */
+ offset -= 16;
+ State.regs[REG_E0 + 0] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_E0 + 1] = load_word (sp + offset);
+ offset -= 4;
+ }
+
+ }
if (mask & 0x80)
{
State.regs[REG_LAR] = load_word (sp + offset);
offset -= 4;
}
+ nia = PC;
}
+
+:include::am33:am33.igen
+