drm/amd/display: Reset DMUB mailbox SW state after HW reset

[Why]
Otherwise we can be out of sync with what's in the hardware, leading
to us rerunning every command that's presently in the ringbuffer.

[How]
Reset software state for the mailboxes in hw_reset callback.
This is already done as part of the mailbox init in hw_init, but we
do need to remember to reset the last cached wptr value as well here.

Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index 4a12292..92c18bf 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -532,6 +532,9 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
        if (dmub->hw_funcs.reset)
                dmub->hw_funcs.reset(dmub);
 
+       /* reset the cache of the last wptr as well now that hw is reset */
+       dmub->inbox1_last_wptr = 0;
+
        cw0.offset.quad_part = inst_fb->gpu_addr;
        cw0.region.base = DMUB_CW0_BASE;
        cw0.region.top = cw0.region.base + inst_fb->size - 1;
@@ -649,6 +652,15 @@ enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub)
        if (dmub->hw_funcs.reset)
                dmub->hw_funcs.reset(dmub);
 
+       /* mailboxes have been reset in hw, so reset the sw state as well */
+       dmub->inbox1_last_wptr = 0;
+       dmub->inbox1_rb.wrpt = 0;
+       dmub->inbox1_rb.rptr = 0;
+       dmub->outbox0_rb.wrpt = 0;
+       dmub->outbox0_rb.rptr = 0;
+       dmub->outbox1_rb.wrpt = 0;
+       dmub->outbox1_rb.rptr = 0;
+
        dmub->hw_init = false;
 
        return DMUB_STATUS_OK;