let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri8")>;
+def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)rr(_REV)?")>;
def: InstRW<[BWWriteResGroup6], (instregex "ADC8rr(_REV)?")>;
def: InstRW<[BWWriteResGroup6], (instregex "ADCX32rr")>;
def: InstRW<[BWWriteResGroup6], (instregex "SAR8ri")>;
def: InstRW<[BWWriteResGroup6], (instregex "SARX32rr")>;
def: InstRW<[BWWriteResGroup6], (instregex "SARX64rr")>;
-def: InstRW<[BWWriteResGroup6], (instregex "SBB(16|32|64)ri8")>;
+def: InstRW<[BWWriteResGroup6], (instregex "SBB(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup6], (instregex "SBB(16|32|64)rr(_REV)?")>;
def: InstRW<[BWWriteResGroup6], (instregex "SBB8rr(_REV)?")>;
def: InstRW<[BWWriteResGroup6], (instregex "SETAEr")>;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[BWWriteResGroup9], (instregex "ADD(16|32|64)ri8")>;
+def: InstRW<[BWWriteResGroup9], (instregex "ADD(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "ADD(16|32|64)rr(_REV)?")>;
def: InstRW<[BWWriteResGroup9], (instregex "ADD8i8")>;
def: InstRW<[BWWriteResGroup9], (instregex "ADD8ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "ADD8rr(_REV)?")>;
-def: InstRW<[BWWriteResGroup9], (instregex "AND(16|32|64)ri8")>;
+def: InstRW<[BWWriteResGroup9], (instregex "AND(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "AND(16|32|64)rr(_REV)?")>;
def: InstRW<[BWWriteResGroup9], (instregex "AND8i8")>;
def: InstRW<[BWWriteResGroup9], (instregex "AND8ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "CBW")>;
def: InstRW<[BWWriteResGroup9], (instregex "CLC")>;
def: InstRW<[BWWriteResGroup9], (instregex "CMC")>;
-def: InstRW<[BWWriteResGroup9], (instregex "CMP(16|32|64)ri8")>;
+def: InstRW<[BWWriteResGroup9], (instregex "CMP(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "CMP(16|32|64)rr(_REV)?")>;
def: InstRW<[BWWriteResGroup9], (instregex "CMP8i8")>;
def: InstRW<[BWWriteResGroup9], (instregex "CMP8ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "NOOP")>;
def: InstRW<[BWWriteResGroup9], (instregex "NOT(16|32|64)r")>;
def: InstRW<[BWWriteResGroup9], (instregex "NOT8r")>;
-def: InstRW<[BWWriteResGroup9], (instregex "OR(16|32|64)ri8")>;
+def: InstRW<[BWWriteResGroup9], (instregex "OR(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "OR(16|32|64)rr(_REV)?")>;
def: InstRW<[BWWriteResGroup9], (instregex "OR8i8")>;
def: InstRW<[BWWriteResGroup9], (instregex "OR8ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "SMSW16m")>;
def: InstRW<[BWWriteResGroup9], (instregex "STC")>;
def: InstRW<[BWWriteResGroup9], (instregex "STRm")>;
-def: InstRW<[BWWriteResGroup9], (instregex "SUB(16|32|64)ri8")>;
+def: InstRW<[BWWriteResGroup9], (instregex "SUB(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "SUB(16|32|64)rr(_REV)?")>;
def: InstRW<[BWWriteResGroup9], (instregex "SUB8i8")>;
def: InstRW<[BWWriteResGroup9], (instregex "SUB8ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "TEST8ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "TEST8rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "XCHG(16|32|64)rr")>;
-def: InstRW<[BWWriteResGroup9], (instregex "XOR(16|32|64)ri8")>;
+def: InstRW<[BWWriteResGroup9], (instregex "XOR(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "XOR(16|32|64)rr(_REV)?")>;
def: InstRW<[BWWriteResGroup9], (instregex "XOR8i8")>;
def: InstRW<[BWWriteResGroup9], (instregex "XOR8ri")>;
def: InstRW<[BWWriteResGroup66], (instregex "ADD8rm")>;
def: InstRW<[BWWriteResGroup66], (instregex "AND(16|32|64)rm")>;
def: InstRW<[BWWriteResGroup66], (instregex "AND8rm")>;
-def: InstRW<[BWWriteResGroup66], (instregex "CMP(16|32|64)mi8")>;
+def: InstRW<[BWWriteResGroup66], (instregex "CMP(16|32|64)mi")>;
def: InstRW<[BWWriteResGroup66], (instregex "CMP(16|32|64)mr")>;
def: InstRW<[BWWriteResGroup66], (instregex "CMP(16|32|64)rm")>;
def: InstRW<[BWWriteResGroup66], (instregex "CMP8mi")>;
let NumMicroOps = 4;
let ResourceCycles = [1,1,1,1];
}
-def: InstRW<[BWWriteResGroup70], (instregex "ADD(16|32|64)mi8")>;
+def: InstRW<[BWWriteResGroup70], (instregex "ADD(16|32|64)mi")>;
def: InstRW<[BWWriteResGroup70], (instregex "ADD(16|32|64)mr")>;
def: InstRW<[BWWriteResGroup70], (instregex "ADD8mi")>;
def: InstRW<[BWWriteResGroup70], (instregex "ADD8mr")>;
-def: InstRW<[BWWriteResGroup70], (instregex "AND(16|32|64)mi8")>;
+def: InstRW<[BWWriteResGroup70], (instregex "AND(16|32|64)mi")>;
def: InstRW<[BWWriteResGroup70], (instregex "AND(16|32|64)mr")>;
def: InstRW<[BWWriteResGroup70], (instregex "AND8mi")>;
def: InstRW<[BWWriteResGroup70], (instregex "AND8mr")>;
def: InstRW<[BWWriteResGroup70], (instregex "NEG8m")>;
def: InstRW<[BWWriteResGroup70], (instregex "NOT(16|32|64)m")>;
def: InstRW<[BWWriteResGroup70], (instregex "NOT8m")>;
-def: InstRW<[BWWriteResGroup70], (instregex "OR(16|32|64)mi8")>;
+def: InstRW<[BWWriteResGroup70], (instregex "OR(16|32|64)mi")>;
def: InstRW<[BWWriteResGroup70], (instregex "OR(16|32|64)mr")>;
def: InstRW<[BWWriteResGroup70], (instregex "OR8mi")>;
def: InstRW<[BWWriteResGroup70], (instregex "OR8mr")>;
def: InstRW<[BWWriteResGroup70], (instregex "POP(16|32|64)rmm")>;
def: InstRW<[BWWriteResGroup70], (instregex "PUSH(16|32|64)rmm")>;
-def: InstRW<[BWWriteResGroup70], (instregex "SUB(16|32|64)mi8")>;
+def: InstRW<[BWWriteResGroup70], (instregex "SUB(16|32|64)mi")>;
def: InstRW<[BWWriteResGroup70], (instregex "SUB(16|32|64)mr")>;
def: InstRW<[BWWriteResGroup70], (instregex "SUB8mi")>;
def: InstRW<[BWWriteResGroup70], (instregex "SUB8mr")>;
-def: InstRW<[BWWriteResGroup70], (instregex "XOR(16|32|64)mi8")>;
+def: InstRW<[BWWriteResGroup70], (instregex "XOR(16|32|64)mi")>;
def: InstRW<[BWWriteResGroup70], (instregex "XOR(16|32|64)mr")>;
def: InstRW<[BWWriteResGroup70], (instregex "XOR8mi")>;
def: InstRW<[BWWriteResGroup70], (instregex "XOR8mr")>;
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,3];
}
-def: InstRW<[BWWriteResGroup99], (instregex "ADC(16|32|64)mi8")>;
+def: InstRW<[BWWriteResGroup99], (instregex "ADC(16|32|64)mi")>;
def: InstRW<[BWWriteResGroup99], (instregex "ADC8mi")>;
def: InstRW<[BWWriteResGroup99], (instregex "ADD8mi")>;
def: InstRW<[BWWriteResGroup99], (instregex "AND8mi")>;
def: InstRW<[BWWriteResGroup100], (instregex "ROL8mCL")>;
def: InstRW<[BWWriteResGroup100], (instregex "SAR(16|32|64)mCL")>;
def: InstRW<[BWWriteResGroup100], (instregex "SAR8mCL")>;
-def: InstRW<[BWWriteResGroup100], (instregex "SBB(16|32|64)mi8")>;
+def: InstRW<[BWWriteResGroup100], (instregex "SBB(16|32|64)mi")>;
def: InstRW<[BWWriteResGroup100], (instregex "SBB(16|32|64)mr")>;
def: InstRW<[BWWriteResGroup100], (instregex "SBB8mi")>;
def: InstRW<[BWWriteResGroup100], (instregex "SBB8mr")>;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[HWWriteResGroup10], (instregex "ADD(16|32|64)ri8")>;
+def: InstRW<[HWWriteResGroup10], (instregex "ADD(16|32|64)ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "ADD(16|32|64)rr(_REV)?")>;
def: InstRW<[HWWriteResGroup10], (instregex "ADD8i8")>;
def: InstRW<[HWWriteResGroup10], (instregex "ADD8ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "ADD8rr(_REV)?")>;
-def: InstRW<[HWWriteResGroup10], (instregex "AND(16|32|64)ri8")>;
+def: InstRW<[HWWriteResGroup10], (instregex "AND(16|32|64)ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "AND(16|32|64)rr(_REV)?")>;
def: InstRW<[HWWriteResGroup10], (instregex "AND8i8")>;
def: InstRW<[HWWriteResGroup10], (instregex "AND8ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "CBW")>;
def: InstRW<[HWWriteResGroup10], (instregex "CLC")>;
def: InstRW<[HWWriteResGroup10], (instregex "CMC")>;
-def: InstRW<[HWWriteResGroup10], (instregex "CMP(16|32|64)ri8")>;
+def: InstRW<[HWWriteResGroup10], (instregex "CMP(16|32|64)ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "CMP(16|32|64)rr(_REV)?")>;
def: InstRW<[HWWriteResGroup10], (instregex "CMP8i8")>;
def: InstRW<[HWWriteResGroup10], (instregex "CMP8ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "NOOP")>;
def: InstRW<[HWWriteResGroup10], (instregex "NOT(16|32|64)r")>;
def: InstRW<[HWWriteResGroup10], (instregex "NOT8r")>;
-def: InstRW<[HWWriteResGroup10], (instregex "OR(16|32|64)ri8")>;
+def: InstRW<[HWWriteResGroup10], (instregex "OR(16|32|64)ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "OR(16|32|64)rr(_REV)?")>;
def: InstRW<[HWWriteResGroup10], (instregex "OR8i8")>;
def: InstRW<[HWWriteResGroup10], (instregex "OR8ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "SMSW16m")>;
def: InstRW<[HWWriteResGroup10], (instregex "STC")>;
def: InstRW<[HWWriteResGroup10], (instregex "STRm")>;
-def: InstRW<[HWWriteResGroup10], (instregex "SUB(16|32|64)ri8")>;
+def: InstRW<[HWWriteResGroup10], (instregex "SUB(16|32|64)ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "SUB(16|32|64)rr(_REV)?")>;
def: InstRW<[HWWriteResGroup10], (instregex "SUB8i8")>;
def: InstRW<[HWWriteResGroup10], (instregex "SUB8ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "TEST8ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "TEST8rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;
-def: InstRW<[HWWriteResGroup10], (instregex "XOR(16|32|64)ri8")>;
+def: InstRW<[HWWriteResGroup10], (instregex "XOR(16|32|64)ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "XOR(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "XOR8i8")>;
def: InstRW<[HWWriteResGroup10], (instregex "XOR8ri")>;
def: InstRW<[HWWriteResGroup18], (instregex "ADD8rm")>;
def: InstRW<[HWWriteResGroup18], (instregex "AND(16|32|64)rm")>;
def: InstRW<[HWWriteResGroup18], (instregex "AND8rm")>;
-def: InstRW<[HWWriteResGroup18], (instregex "CMP(16|32|64)mi8")>;
+def: InstRW<[HWWriteResGroup18], (instregex "CMP(16|32|64)mi")>;
def: InstRW<[HWWriteResGroup18], (instregex "CMP(16|32|64)mr")>;
def: InstRW<[HWWriteResGroup18], (instregex "CMP(16|32|64)rm")>;
def: InstRW<[HWWriteResGroup18], (instregex "CMP8mi")>;
let NumMicroOps = 4;
let ResourceCycles = [1,1,1,1];
}
-def: InstRW<[HWWriteResGroup26], (instregex "ADD(16|32|64)mi8")>;
+def: InstRW<[HWWriteResGroup26], (instregex "ADD(16|32|64)mi")>;
def: InstRW<[HWWriteResGroup26], (instregex "ADD(16|32|64)mr")>;
def: InstRW<[HWWriteResGroup26], (instregex "ADD8mi")>;
def: InstRW<[HWWriteResGroup26], (instregex "ADD8mr")>;
-def: InstRW<[HWWriteResGroup26], (instregex "AND(16|32|64)mi8")>;
+def: InstRW<[HWWriteResGroup26], (instregex "AND(16|32|64)mi")>;
def: InstRW<[HWWriteResGroup26], (instregex "AND(16|32|64)mr")>;
def: InstRW<[HWWriteResGroup26], (instregex "AND8mi")>;
def: InstRW<[HWWriteResGroup26], (instregex "AND8mr")>;
def: InstRW<[HWWriteResGroup26], (instregex "NEG8m")>;
def: InstRW<[HWWriteResGroup26], (instregex "NOT(16|32|64)m")>;
def: InstRW<[HWWriteResGroup26], (instregex "NOT8m")>;
-def: InstRW<[HWWriteResGroup26], (instregex "OR(16|32|64)mi8")>;
+def: InstRW<[HWWriteResGroup26], (instregex "OR(16|32|64)mi")>;
def: InstRW<[HWWriteResGroup26], (instregex "OR(16|32|64)mr")>;
def: InstRW<[HWWriteResGroup26], (instregex "OR8mi")>;
def: InstRW<[HWWriteResGroup26], (instregex "OR8mr")>;
def: InstRW<[HWWriteResGroup26], (instregex "POP(16|32|64)rmm")>;
def: InstRW<[HWWriteResGroup26], (instregex "PUSH(16|32|64)rmm")>;
-def: InstRW<[HWWriteResGroup26], (instregex "SUB(16|32|64)mi8")>;
+def: InstRW<[HWWriteResGroup26], (instregex "SUB(16|32|64)mi")>;
def: InstRW<[HWWriteResGroup26], (instregex "SUB(16|32|64)mr")>;
def: InstRW<[HWWriteResGroup26], (instregex "SUB8mi")>;
def: InstRW<[HWWriteResGroup26], (instregex "SUB8mr")>;
-def: InstRW<[HWWriteResGroup26], (instregex "XOR(16|32|64)mi8")>;
+def: InstRW<[HWWriteResGroup26], (instregex "XOR(16|32|64)mi")>;
def: InstRW<[HWWriteResGroup26], (instregex "XOR(16|32|64)mr")>;
def: InstRW<[HWWriteResGroup26], (instregex "XOR8mi")>;
def: InstRW<[HWWriteResGroup26], (instregex "XOR8mr")>;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[HWWriteResGroup35], (instregex "ADC(16|32|64)ri8")>;
+def: InstRW<[HWWriteResGroup35], (instregex "ADC(16|32|64)ri")>;
def: InstRW<[HWWriteResGroup35], (instregex "ADC(16|32|64)rr(_REV)?")>;
def: InstRW<[HWWriteResGroup35], (instregex "ADC8i8")>;
def: InstRW<[HWWriteResGroup35], (instregex "ADC8ri")>;
def: InstRW<[HWWriteResGroup35], (instregex "CMOVS(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup35], (instregex "CWD")>;
def: InstRW<[HWWriteResGroup35], (instregex "JRCXZ")>;
-def: InstRW<[HWWriteResGroup35], (instregex "SBB(16|32|64)ri8")>;
+def: InstRW<[HWWriteResGroup35], (instregex "SBB(16|32|64)ri")>;
def: InstRW<[HWWriteResGroup35], (instregex "SBB(16|32|64)rr(_REV)?")>;
def: InstRW<[HWWriteResGroup35], (instregex "SBB8i8")>;
def: InstRW<[HWWriteResGroup35], (instregex "SBB8ri")>;
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,3];
}
-def: InstRW<[HWWriteResGroup68], (instregex "ADC(16|32|64)mi8")>;
+def: InstRW<[HWWriteResGroup68], (instregex "ADC(16|32|64)mi")>;
def: InstRW<[HWWriteResGroup68], (instregex "ADC8mi")>;
def: InstRW<[HWWriteResGroup68], (instregex "ADD8mi")>;
def: InstRW<[HWWriteResGroup68], (instregex "AND8mi")>;
def: InstRW<[HWWriteResGroup69], (instregex "ROL8mCL")>;
def: InstRW<[HWWriteResGroup69], (instregex "SAR(16|32|64)mCL")>;
def: InstRW<[HWWriteResGroup69], (instregex "SAR8mCL")>;
-def: InstRW<[HWWriteResGroup69], (instregex "SBB(16|32|64)mi8")>;
+def: InstRW<[HWWriteResGroup69], (instregex "SBB(16|32|64)mi")>;
def: InstRW<[HWWriteResGroup69], (instregex "SBB(16|32|64)mr")>;
def: InstRW<[HWWriteResGroup69], (instregex "SBB8mi")>;
def: InstRW<[HWWriteResGroup69], (instregex "SBB8mr")>;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SBWriteResGroup6], (instregex "ADD(16|32|64)ri8")>;
+def: InstRW<[SBWriteResGroup6], (instregex "ADD(16|32|64)ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "ADD(16|32|64)rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "ADD8i8")>;
def: InstRW<[SBWriteResGroup6], (instregex "ADD8ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "ADD8rr")>;
-def: InstRW<[SBWriteResGroup6], (instregex "AND(16|32|64)ri8")>;
+def: InstRW<[SBWriteResGroup6], (instregex "AND(16|32|64)ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "AND(16|32|64)rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "AND8i8")>;
def: InstRW<[SBWriteResGroup6], (instregex "AND8ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "AND8rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "CBW")>;
def: InstRW<[SBWriteResGroup6], (instregex "CMC")>;
-def: InstRW<[SBWriteResGroup6], (instregex "CMP(16|32|64)ri8")>;
+def: InstRW<[SBWriteResGroup6], (instregex "CMP(16|32|64)ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "CMP(16|32|64)rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "CMP8i8")>;
def: InstRW<[SBWriteResGroup6], (instregex "CMP8ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "NEG8r")>;
def: InstRW<[SBWriteResGroup6], (instregex "NOT(16|32|64)r")>;
def: InstRW<[SBWriteResGroup6], (instregex "NOT8r")>;
-def: InstRW<[SBWriteResGroup6], (instregex "OR(16|32|64)ri8")>;
+def: InstRW<[SBWriteResGroup6], (instregex "OR(16|32|64)ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "OR(16|32|64)rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "OR8i8")>;
def: InstRW<[SBWriteResGroup6], (instregex "OR8ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "PORrr")>;
def: InstRW<[SBWriteResGroup6], (instregex "PXORrr")>;
def: InstRW<[SBWriteResGroup6], (instregex "STC")>;
-def: InstRW<[SBWriteResGroup6], (instregex "SUB(16|32|64)ri8")>;
+def: InstRW<[SBWriteResGroup6], (instregex "SUB(16|32|64)ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "SUB(16|32|64)rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "SUB8i8")>;
def: InstRW<[SBWriteResGroup6], (instregex "SUB8ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "VPANDrr")>;
def: InstRW<[SBWriteResGroup6], (instregex "VPORrr")>;
def: InstRW<[SBWriteResGroup6], (instregex "VPXORrr")>;
-def: InstRW<[SBWriteResGroup6], (instregex "XOR(16|32|64)ri8")>;
+def: InstRW<[SBWriteResGroup6], (instregex "XOR(16|32|64)ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "XOR(16|32|64)rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "XOR8i8")>;
def: InstRW<[SBWriteResGroup6], (instregex "XOR8ri")>;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup19], (instregex "ADC(16|32|64)ri8")>;
+def: InstRW<[SBWriteResGroup19], (instregex "ADC(16|32|64)ri")>;
def: InstRW<[SBWriteResGroup19], (instregex "ADC(16|32|64)rr")>;
def: InstRW<[SBWriteResGroup19], (instregex "ADC8ri")>;
def: InstRW<[SBWriteResGroup19], (instregex "ADC8rr")>;
def: InstRW<[SBWriteResGroup19], (instregex "CMOVO(16|32|64)rr")>;
def: InstRW<[SBWriteResGroup19], (instregex "CMOVP(16|32|64)rr")>;
def: InstRW<[SBWriteResGroup19], (instregex "CMOVS(16|32|64)rr")>;
-def: InstRW<[SBWriteResGroup19], (instregex "SBB(16|32|64)ri8")>;
+def: InstRW<[SBWriteResGroup19], (instregex "SBB(16|32|64)ri")>;
def: InstRW<[SBWriteResGroup19], (instregex "SBB(16|32|64)rr")>;
def: InstRW<[SBWriteResGroup19], (instregex "SBB8ri")>;
def: InstRW<[SBWriteResGroup19], (instregex "SBB8rr")>;
def: InstRW<[SBWriteResGroup52], (instregex "ADD8rm")>;
def: InstRW<[SBWriteResGroup52], (instregex "AND(16|32|64)rm")>;
def: InstRW<[SBWriteResGroup52], (instregex "AND8rm")>;
-def: InstRW<[SBWriteResGroup52], (instregex "CMP(16|32|64)mi8")>;
+def: InstRW<[SBWriteResGroup52], (instregex "CMP(16|32|64)mi")>;
def: InstRW<[SBWriteResGroup52], (instregex "CMP(16|32|64)mr")>;
def: InstRW<[SBWriteResGroup52], (instregex "CMP(16|32|64)rm")>;
def: InstRW<[SBWriteResGroup52], (instregex "CMP8mi")>;
let NumMicroOps = 4;
let ResourceCycles = [1,2,1];
}
-def: InstRW<[SBWriteResGroup70], (instregex "ADD(16|32|64)mi8")>;
+def: InstRW<[SBWriteResGroup70], (instregex "ADD(16|32|64)mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "ADD(16|32|64)mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "ADD8mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "ADD8mr")>;
-def: InstRW<[SBWriteResGroup70], (instregex "AND(16|32|64)mi8")>;
+def: InstRW<[SBWriteResGroup70], (instregex "AND(16|32|64)mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "AND(16|32|64)mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "AND8mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "AND8mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "NEG8m")>;
def: InstRW<[SBWriteResGroup70], (instregex "NOT(16|32|64)m")>;
def: InstRW<[SBWriteResGroup70], (instregex "NOT8m")>;
-def: InstRW<[SBWriteResGroup70], (instregex "OR(16|32|64)mi8")>;
+def: InstRW<[SBWriteResGroup70], (instregex "OR(16|32|64)mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "OR(16|32|64)mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "OR8mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "OR8mr")>;
-def: InstRW<[SBWriteResGroup70], (instregex "SUB(16|32|64)mi8")>;
+def: InstRW<[SBWriteResGroup70], (instregex "SUB(16|32|64)mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "SUB(16|32|64)mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "SUB8mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "SUB8mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "TEST(16|32|64)mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "TEST8mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "TEST8mr")>;
-def: InstRW<[SBWriteResGroup70], (instregex "XOR(16|32|64)mi8")>;
+def: InstRW<[SBWriteResGroup70], (instregex "XOR(16|32|64)mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "XOR(16|32|64)mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "XOR8mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "XOR8mr")>;
let NumMicroOps = 6;
let ResourceCycles = [1,2,3];
}
-def: InstRW<[SBWriteResGroup98], (instregex "ADC(16|32|64)mi8")>;
+def: InstRW<[SBWriteResGroup98], (instregex "ADC(16|32|64)mi")>;
def: InstRW<[SBWriteResGroup98], (instregex "ADC8mi")>;
-def: InstRW<[SBWriteResGroup98], (instregex "SBB(16|32|64)mi8")>;
+def: InstRW<[SBWriteResGroup98], (instregex "SBB(16|32|64)mi")>;
def: InstRW<[SBWriteResGroup98], (instregex "SBB8mi")>;
def SBWriteResGroup99 : SchedWriteRes<[SBPort4,SBPort23,SBPort05,SBPort015]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup7], (instregex "ADC8rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup7], (instregex "ADCX32rr")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SAR8ri")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SARX32rr")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SARX64rr")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "SBB(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SBB(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SBB(16|32|64)rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SBB8rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SETAEr")>;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup10], (instregex "ADD(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "ADD(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "ADD(16|32|64)rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup10], (instregex "ADD8i8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "ADD8ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "ADD8rr(_REV)?")>;
-def: InstRW<[SKLWriteResGroup10], (instregex "AND(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "AND(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "AND(16|32|64)rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup10], (instregex "AND8i8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "AND8ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "CBW")>;
def: InstRW<[SKLWriteResGroup10], (instregex "CLC")>;
def: InstRW<[SKLWriteResGroup10], (instregex "CMC")>;
-def: InstRW<[SKLWriteResGroup10], (instregex "CMP(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "CMP(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "CMP(16|32|64)rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup10], (instregex "CMP8i8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "CMP8ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "NOOP")>;
def: InstRW<[SKLWriteResGroup10], (instregex "NOT(16|32|64)r")>;
def: InstRW<[SKLWriteResGroup10], (instregex "NOT8r")>;
-def: InstRW<[SKLWriteResGroup10], (instregex "OR(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "OR(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "OR(16|32|64)rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup10], (instregex "OR8i8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "OR8ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SMSW16m")>;
def: InstRW<[SKLWriteResGroup10], (instregex "STC")>;
def: InstRW<[SKLWriteResGroup10], (instregex "STRm")>;
-def: InstRW<[SKLWriteResGroup10], (instregex "SUB(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "SUB(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SUB(16|32|64)rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SUB8i8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SUB8ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "TEST8ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "TEST8rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup10], (instregex "XOR(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "XOR(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "XOR(16|32|64)rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup10], (instregex "XOR8i8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "XOR8ri")>;
def: InstRW<[SKLWriteResGroup76], (instregex "ADD8rm")>;
def: InstRW<[SKLWriteResGroup76], (instregex "AND(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup76], (instregex "AND8rm")>;
-def: InstRW<[SKLWriteResGroup76], (instregex "CMP(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "CMP(16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup76], (instregex "CMP(16|32|64)mr")>;
def: InstRW<[SKLWriteResGroup76], (instregex "CMP(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup76], (instregex "CMP8mi")>;
let NumMicroOps = 4;
let ResourceCycles = [1,1,1,1];
}
-def: InstRW<[SKLWriteResGroup83], (instregex "ADD(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "ADD(16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup83], (instregex "ADD(16|32|64)mr")>;
def: InstRW<[SKLWriteResGroup83], (instregex "ADD8mi")>;
def: InstRW<[SKLWriteResGroup83], (instregex "ADD8mr")>;
-def: InstRW<[SKLWriteResGroup83], (instregex "AND(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "AND(16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup83], (instregex "AND(16|32|64)mr")>;
def: InstRW<[SKLWriteResGroup83], (instregex "AND8mi")>;
def: InstRW<[SKLWriteResGroup83], (instregex "AND8mr")>;
def: InstRW<[SKLWriteResGroup83], (instregex "NEG8m")>;
def: InstRW<[SKLWriteResGroup83], (instregex "NOT(16|32|64)m")>;
def: InstRW<[SKLWriteResGroup83], (instregex "NOT8m")>;
-def: InstRW<[SKLWriteResGroup83], (instregex "OR(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "OR(16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup83], (instregex "OR(16|32|64)mr")>;
def: InstRW<[SKLWriteResGroup83], (instregex "OR8mi")>;
def: InstRW<[SKLWriteResGroup83], (instregex "OR8mr")>;
def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm")>;
def: InstRW<[SKLWriteResGroup83], (instregex "PUSH(16|32|64)rmm")>;
-def: InstRW<[SKLWriteResGroup83], (instregex "SUB(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "SUB(16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup83], (instregex "SUB(16|32|64)mr")>;
def: InstRW<[SKLWriteResGroup83], (instregex "SUB8mi")>;
def: InstRW<[SKLWriteResGroup83], (instregex "SUB8mr")>;
-def: InstRW<[SKLWriteResGroup83], (instregex "XOR(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "XOR(16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup83], (instregex "XOR(16|32|64)mr")>;
def: InstRW<[SKLWriteResGroup83], (instregex "XOR8mi")>;
def: InstRW<[SKLWriteResGroup83], (instregex "XOR8mr")>;
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,3];
}
-def: InstRW<[SKLWriteResGroup118], (instregex "ADC(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup118], (instregex "ADC(16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup118], (instregex "ADC8mi")>;
def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
def: InstRW<[SKLWriteResGroup119], (instregex "ADC8mr")>;
def: InstRW<[SKLWriteResGroup119], (instregex "CMPXCHG(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup119], (instregex "CMPXCHG8rm")>;
-def: InstRW<[SKLWriteResGroup119], (instregex "SBB(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup119], (instregex "SBB(16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup119], (instregex "SBB(16|32|64)mr")>;
def: InstRW<[SKLWriteResGroup119], (instregex "SBB8mi")>;
def: InstRW<[SKLWriteResGroup119], (instregex "SBB8mr")>;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)ri8")>;
+def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup7], (instregex "ADC8rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup7], (instregex "ADCX32rr")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SAR8ri")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SARX32rr")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SARX64rr")>;
-def: InstRW<[SKXWriteResGroup7], (instregex "SBB(16|32|64)ri8")>;
+def: InstRW<[SKXWriteResGroup7], (instregex "SBB(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SBB(16|32|64)rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SBB8rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SETAEr")>;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKXWriteResGroup10], (instregex "ADD(16|32|64)ri8")>;
+def: InstRW<[SKXWriteResGroup10], (instregex "ADD(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "ADD(16|32|64)rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup10], (instregex "ADD8i8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "ADD8ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "ADD8rr(_REV)?")>;
-def: InstRW<[SKXWriteResGroup10], (instregex "AND(16|32|64)ri8")>;
+def: InstRW<[SKXWriteResGroup10], (instregex "AND(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "AND(16|32|64)rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup10], (instregex "AND8i8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "AND8ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "CBW")>;
def: InstRW<[SKXWriteResGroup10], (instregex "CLC")>;
def: InstRW<[SKXWriteResGroup10], (instregex "CMC")>;
-def: InstRW<[SKXWriteResGroup10], (instregex "CMP(16|32|64)ri8")>;
+def: InstRW<[SKXWriteResGroup10], (instregex "CMP(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "CMP(16|32|64)rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup10], (instregex "CMP8i8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "CMP8ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "NOOP")>;
def: InstRW<[SKXWriteResGroup10], (instregex "NOT(16|32|64)r")>;
def: InstRW<[SKXWriteResGroup10], (instregex "NOT8r")>;
-def: InstRW<[SKXWriteResGroup10], (instregex "OR(16|32|64)ri8")>;
+def: InstRW<[SKXWriteResGroup10], (instregex "OR(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "OR(16|32|64)rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup10], (instregex "OR8i8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "OR8ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SMSW16m")>;
def: InstRW<[SKXWriteResGroup10], (instregex "STC")>;
def: InstRW<[SKXWriteResGroup10], (instregex "STRm")>;
-def: InstRW<[SKXWriteResGroup10], (instregex "SUB(16|32|64)ri8")>;
+def: InstRW<[SKXWriteResGroup10], (instregex "SUB(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SUB(16|32|64)rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SUB8i8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SUB8ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "TEST8ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "TEST8rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;
-def: InstRW<[SKXWriteResGroup10], (instregex "XOR(16|32|64)ri8")>;
+def: InstRW<[SKXWriteResGroup10], (instregex "XOR(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "XOR(16|32|64)rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup10], (instregex "XOR8i8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "XOR8ri")>;
def: InstRW<[SKXWriteResGroup81], (instregex "ADD8rm")>;
def: InstRW<[SKXWriteResGroup81], (instregex "AND(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup81], (instregex "AND8rm")>;
-def: InstRW<[SKXWriteResGroup81], (instregex "CMP(16|32|64)mi8")>;
+def: InstRW<[SKXWriteResGroup81], (instregex "CMP(16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup81], (instregex "CMP(16|32|64)mr")>;
def: InstRW<[SKXWriteResGroup81], (instregex "CMP(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup81], (instregex "CMP8mi")>;
let NumMicroOps = 4;
let ResourceCycles = [1,1,1,1];
}
-def: InstRW<[SKXWriteResGroup87], (instregex "ADD(16|32|64)mi8")>;
+def: InstRW<[SKXWriteResGroup87], (instregex "ADD(16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup87], (instregex "ADD(16|32|64)mr")>;
def: InstRW<[SKXWriteResGroup87], (instregex "ADD8mi")>;
def: InstRW<[SKXWriteResGroup87], (instregex "ADD8mr")>;
-def: InstRW<[SKXWriteResGroup87], (instregex "AND(16|32|64)mi8")>;
+def: InstRW<[SKXWriteResGroup87], (instregex "AND(16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup87], (instregex "AND(16|32|64)mr")>;
def: InstRW<[SKXWriteResGroup87], (instregex "AND8mi")>;
def: InstRW<[SKXWriteResGroup87], (instregex "AND8mr")>;
def: InstRW<[SKXWriteResGroup87], (instregex "NEG8m")>;
def: InstRW<[SKXWriteResGroup87], (instregex "NOT(16|32|64)m")>;
def: InstRW<[SKXWriteResGroup87], (instregex "NOT8m")>;
-def: InstRW<[SKXWriteResGroup87], (instregex "OR(16|32|64)mi8")>;
+def: InstRW<[SKXWriteResGroup87], (instregex "OR(16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup87], (instregex "OR(16|32|64)mr")>;
def: InstRW<[SKXWriteResGroup87], (instregex "OR8mi")>;
def: InstRW<[SKXWriteResGroup87], (instregex "OR8mr")>;
def: InstRW<[SKXWriteResGroup87], (instregex "POP(16|32|64)rmm")>;
def: InstRW<[SKXWriteResGroup87], (instregex "PUSH(16|32|64)rmm")>;
-def: InstRW<[SKXWriteResGroup87], (instregex "SUB(16|32|64)mi8")>;
+def: InstRW<[SKXWriteResGroup87], (instregex "SUB(16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup87], (instregex "SUB(16|32|64)mr")>;
def: InstRW<[SKXWriteResGroup87], (instregex "SUB8mi")>;
def: InstRW<[SKXWriteResGroup87], (instregex "SUB8mr")>;
-def: InstRW<[SKXWriteResGroup87], (instregex "XOR(16|32|64)mi8")>;
+def: InstRW<[SKXWriteResGroup87], (instregex "XOR(16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup87], (instregex "XOR(16|32|64)mr")>;
def: InstRW<[SKXWriteResGroup87], (instregex "XOR8mi")>;
def: InstRW<[SKXWriteResGroup87], (instregex "XOR8mr")>;
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,3];
}
-def: InstRW<[SKXWriteResGroup129], (instregex "ADC(16|32|64)mi8")>;
+def: InstRW<[SKXWriteResGroup129], (instregex "ADC(16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup129], (instregex "ADC8mi")>;
def SKXWriteResGroup130 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
def: InstRW<[SKXWriteResGroup130], (instregex "ADC8mr")>;
def: InstRW<[SKXWriteResGroup130], (instregex "CMPXCHG(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup130], (instregex "CMPXCHG8rm")>;
-def: InstRW<[SKXWriteResGroup130], (instregex "SBB(16|32|64)mi8")>;
+def: InstRW<[SKXWriteResGroup130], (instregex "SBB(16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup130], (instregex "SBB(16|32|64)mr")>;
def: InstRW<[SKXWriteResGroup130], (instregex "SBB8mi")>;
def: InstRW<[SKXWriteResGroup130], (instregex "SBB8mr")>;