[Hexagon] Disable packets in test to avoid ordering issues in checks

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337624 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/Hexagon/vec-call-full1.ll b/test/CodeGen/Hexagon/vec-call-full1.ll
index d8f562e..24cc975 100644 (file)
--- a/test/CodeGen/Hexagon/vec-call-full1.ll
+++ b/test/CodeGen/Hexagon/vec-call-full1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
+; RUN: llc -march=hexagon < %s | FileCheck %s
 
 ; CHECK-DAG: v{{[0-9]+}} = vmem(r{{[0-9]+}}+#0)
 ; CHECK-DAG: v{{[0-9]+}} = vmem(r{{[0-9]+}}+#0)
@@ -16,4 +16,4 @@ b0:
 
 declare void @f1(<32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>) #0
 
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b,-packets" }