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drm/amdkfd: Update packet manager for GFX9.4.3
authorMukul Joshi <mukul.joshi@amd.com>
Thu, 8 Dec 2022 17:08:17 +0000 (12:08 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 9 Jun 2023 13:50:19 +0000 (09:50 -0400)
In GFX 9.4.3, there can be more than 8 SDMA engines.
As a result, extended_engine_sel and engine_sel fields
in MAP_QUEUES packet need to be updated to allow correct
mapping of SDMA queues to these SDMA engines.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c
drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h

index 54d7d46..44cf3a5 100644 (file)
@@ -225,9 +225,19 @@ static int pm_map_queues_v9(struct packet_manager *pm, uint32_t *buffer,
                        packet->bitfields2.engine_sel = q->properties.sdma_engine_id +
                                engine_sel__mes_map_queues__sdma0_vi;
                else {
-                       packet->bitfields2.extended_engine_sel =
-                               extended_engine_sel__mes_map_queues__sdma0_to_7_sel;
-                       packet->bitfields2.engine_sel = q->properties.sdma_engine_id;
+                       /*
+                        * For GFX9.4.3, SDMA engine id can be greater than 8.
+                        * For such cases, set extended_engine_sel to 2 and
+                        * ensure engine_sel lies between 0-7.
+                        */
+                       if (q->properties.sdma_engine_id >= 8)
+                               packet->bitfields2.extended_engine_sel =
+                                       extended_engine_sel__mes_map_queues__sdma8_to_15_sel;
+                       else
+                               packet->bitfields2.extended_engine_sel =
+                                       extended_engine_sel__mes_map_queues__sdma0_to_7_sel;
+
+                       packet->bitfields2.engine_sel = q->properties.sdma_engine_id % 8;
                }
                break;
        default:
index a666710..2ad708c 100644 (file)
@@ -263,7 +263,8 @@ enum mes_map_queues_engine_sel_enum {
 
 enum mes_map_queues_extended_engine_sel_enum {
        extended_engine_sel__mes_map_queues__legacy_engine_sel = 0,
-       extended_engine_sel__mes_map_queues__sdma0_to_7_sel = 1
+       extended_engine_sel__mes_map_queues__sdma0_to_7_sel  = 1,
+       extended_engine_sel__mes_map_queues__sdma8_to_15_sel = 2
 };
 
 struct pm4_mes_map_queues {