arm64: dts: qcom: sm6350: Add SDHCI1/2 nodes

Add SDHCI1/2 nodes for eMMC and uSD card respectively.
Do note that most SM6350 devices seem to come with UFS.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
[bjorn: Replaced SM6350_CX with its constant value]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210923162204.21752-14-konrad.dybcio@somainline.org

diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 55a5337..cbe355b 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 
 / {
@@ -397,12 +398,92 @@
                        clock-names = "core";
                };
 
+               sdhc_1: sdhci@7c4000 {
+                       compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
+                       reg = <0 0x007c4000 0 0x1000>,
+                               <0 0x007c5000 0 0x1000>,
+                               <0 0x007c8000 0 0x8000>;
+                       reg-names = "hc", "cqhci", "ice";
+
+                       interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "hc_irq", "pwr_irq";
+
+                       clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+                                <&gcc GCC_SDCC1_APPS_CLK>,
+                                <&rpmhcc RPMH_CXO_CLK>;
+                       clock-names = "iface", "core", "xo";
+                       qcom,dll-config = <0x000f642c>;
+                       qcom,ddr-config = <0x80040868>;
+                       power-domains = <&rpmhpd 0>;
+                       operating-points-v2 = <&sdhc1_opp_table>;
+                       bus-width = <8>;
+                       non-removable;
+                       supports-cqe;
+
+                       status = "disabled";
+
+                       sdhc1_opp_table: sdhc1-opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-19200000 {
+                                       opp-hz = /bits/ 64 <19200000>;
+                                       required-opps = <&rpmhpd_opp_min_svs>;
+                               };
+
+                               opp-100000000 {
+                                       opp-hz = /bits/ 64 <100000000>;
+                                       required-opps = <&rpmhpd_opp_low_svs>;
+                               };
+
+                               opp-384000000 {
+                                       opp-hz = /bits/ 64 <384000000>;
+                                       required-opps = <&rpmhpd_opp_svs_l1>;
+                               };
+                       };
+               };
+
                tcsr_mutex: hwlock@1f40000 {
                        compatible = "qcom,tcsr-mutex";
                        reg = <0x0 0x01f40000 0x0 0x40000>;
                        #hwlock-cells = <1>;
                };
 
+               sdhc_2: sdhci@8804000 {
+                       compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
+                       reg = <0 0x08804000 0 0x1000>;
+
+                       interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "hc_irq", "pwr_irq";
+
+                       clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+                                <&gcc GCC_SDCC2_APPS_CLK>,
+                                <&rpmhcc RPMH_CXO_CLK>;
+                       clock-names = "iface", "core", "xo";
+                       qcom,dll-config = <0x0007642c>;
+                       qcom,ddr-config = <0x80040868>;
+                       power-domains = <&rpmhpd 0>;
+                       operating-points-v2 = <&sdhc2_opp_table>;
+                       bus-width = <4>;
+
+                       status = "disabled";
+
+                       sdhc2_opp_table: sdhc2-opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-100000000 {
+                                       opp-hz = /bits/ 64 <100000000>;
+                                       required-opps = <&rpmhpd_opp_svs_l1>;
+                               };
+
+                               opp-202000000 {
+                                       opp-hz = /bits/ 64 <202000000>;
+                                       required-opps = <&rpmhpd_opp_nom>;
+                               };
+                       };
+               };
+
                usb_1_hsphy: phy@88e3000 {
                        compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy";
                        reg = <0 0x088e3000 0 0x400>;