drm/amdgpu: Remove programming GCMC_VM_FB_LOCATION* on gfxhub_v3_0_3 in VF

[Why]
GCMC_VM related registers should be programmed by PSP on host side.
L1 and RLCG will block these regisers on VF.

[How]
Remove programming GCMC_VM_FB_LOCATION_BASE/TOP on gfxhub_v3_0_3 under SRIOV VF.

Signed-off-by: Yifan Zha <Yifan.Zha@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c
index 716ae6f..080ff11 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c
@@ -357,18 +357,6 @@ static void gfxhub_v3_0_3_program_invalidation(struct amdgpu_device *adev)
 
 static int gfxhub_v3_0_3_gart_enable(struct amdgpu_device *adev)
 {
-       if (amdgpu_sriov_vf(adev)) {
-               /*
-                * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
-                * VF copy registers so vbios post doesn't program them, for
-                * SRIOV driver need to program them
-                */
-               WREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE,
-                            adev->gmc.vram_start >> 24);
-               WREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_TOP,
-                            adev->gmc.vram_end >> 24);
-       }
-
        /* GART Enable. */
        gfxhub_v3_0_3_init_gart_aperture_regs(adev);
        gfxhub_v3_0_3_init_system_aperture_regs(adev);