intel/genxml: Add SO_WRITE_OFFSET registers for gen7-9

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 9bb8633..9d52aac 100644 (file)
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -2565,4 +2565,20 @@
     <field name="T Low Bandwidth" start="21" end="21" type="uint"/>
   </register>
 
+  <register name="SO_WRITE_OFFSET0" length="1" num="0x5280">
+    <field name="Write Offset" start="2" end="31" type="offset"/>
+  </register>
+
+  <register name="SO_WRITE_OFFSET1" length="1" num="0x5284">
+    <field name="Write Offset" start="2" end="31" type="offset"/>
+  </register>
+
+  <register name="SO_WRITE_OFFSET2" length="1" num="0x5288">
+    <field name="Write Offset" start="2" end="31" type="offset"/>
+  </register>
+
+  <register name="SO_WRITE_OFFSET3" length="1" num="0x528c">
+    <field name="Write Offset" start="2" end="31" type="offset"/>
+  </register>
+
 </genxml>

diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index eb00c15..ab8bec6 100644 (file)
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -2981,4 +2981,20 @@
     <field name="L3 Atomic Disable Mask" start="22" end="22" type="uint"/>
   </register>
 
+  <register name="SO_WRITE_OFFSET0" length="1" num="0x5280">
+    <field name="Write Offset" start="2" end="31" type="offset"/>
+  </register>
+
+  <register name="SO_WRITE_OFFSET1" length="1" num="0x5284">
+    <field name="Write Offset" start="2" end="31" type="offset"/>
+  </register>
+
+  <register name="SO_WRITE_OFFSET2" length="1" num="0x5288">
+    <field name="Write Offset" start="2" end="31" type="offset"/>
+  </register>
+
+  <register name="SO_WRITE_OFFSET3" length="1" num="0x528c">
+    <field name="Write Offset" start="2" end="31" type="offset"/>
+  </register>
+
 </genxml>

diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 3178b1d..1fbf6d8 100644 (file)
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -3175,4 +3175,20 @@
     <field name="All Allocation" start="25" end="31" type="uint"/>
   </register>
 
+  <register name="SO_WRITE_OFFSET0" length="1" num="0x5280">
+    <field name="Write Offset" start="2" end="31" type="offset"/>
+  </register>
+
+  <register name="SO_WRITE_OFFSET1" length="1" num="0x5284">
+    <field name="Write Offset" start="2" end="31" type="offset"/>
+  </register>
+
+  <register name="SO_WRITE_OFFSET2" length="1" num="0x5288">
+    <field name="Write Offset" start="2" end="31" type="offset"/>
+  </register>
+
+  <register name="SO_WRITE_OFFSET3" length="1" num="0x528c">
+    <field name="Write Offset" start="2" end="31" type="offset"/>
+  </register>
+
 </genxml>

diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 3d44cdb..46b1ced 100644 (file)
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -3449,4 +3449,20 @@
     <field name="All Allocation" start="25" end="31" type="uint"/>
   </register>
 
+  <register name="SO_WRITE_OFFSET0" length="1" num="0x5280">
+    <field name="Write Offset" start="2" end="31" type="offset"/>
+  </register>
+
+  <register name="SO_WRITE_OFFSET1" length="1" num="0x5284">
+    <field name="Write Offset" start="2" end="31" type="offset"/>
+  </register>
+
+  <register name="SO_WRITE_OFFSET2" length="1" num="0x5288">
+    <field name="Write Offset" start="2" end="31" type="offset"/>
+  </register>
+
+  <register name="SO_WRITE_OFFSET3" length="1" num="0x528c">
+    <field name="Write Offset" start="2" end="31" type="offset"/>
+  </register>
+
 </genxml>