simple architecture deployed...

diff --git a/simulation/cpu/Makefile b/simulation/cpu/Makefile
index feb70c4..3a1f5d9 100644 (file)
--- a/simulation/cpu/Makefile
+++ b/simulation/cpu/Makefile
@@ -1,6 +1,5 @@
 
-MODULES=pc.vhd decoder.vhd data_latch.vhd \
-               mos6502.vhd 
+MODULES= mos6502.vhd 
                #cpu_timing.vhd 
 
 TEST_MODULE= testbench_mos6502.vhd

diff --git a/simulation/cpu/data_latch.vhd b/simulation/cpu/data_latch.vhd
deleted file mode 100644 (file)
index ae9ba1b..0000000
--- a/simulation/cpu/data_latch.vhd
+++ /dev/null
@@ -1,21 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity data_latch is 
-    generic (dsize : integer := 8);
-    port (  clk, en     : in std_logic;
-            d           : in std_logic_vector (dsize - 1 downto 0);
-            q           : out std_logic_vector (dsize - 1 downto 0)
-        );
-end data_latch;
-
-architecture rtl of data_latch is
-begin
-    p : process (clk, d)
-    begin
-    if (clk= '1' and en = '1') then
-        q <= d;
-    end if;
-    end process;
-end rtl;
-

diff --git a/simulation/cpu/decoder.vhd b/simulation/cpu/decoder.vhd
deleted file mode 100644 (file)
index 60769cc..0000000
--- a/simulation/cpu/decoder.vhd
+++ /dev/null
@@ -1,71 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
---use ieee.std_logic_arith.all;
-
-entity decoder is 
-    generic (dsize : integer := 8);
-    port (  set_clk         : in std_logic;
-            trig_clk        : in std_logic;
-            res_n           : in std_logic;
-            irq_n           : in std_logic;
-            nmi_n           : in std_logic;
-            rdy             : in std_logic;
-            instruction     : in std_logic_vector (dsize - 1 downto 0);
-            status_reg      : in std_logic_vector (dsize - 1 downto 0);
-            pcl_d_i_n       : out std_logic;
-            pcl_d_o_n       : out std_logic;
-            pcl_a_o_n       : out std_logic;
-            pch_d_i_n       : out std_logic;
-            pch_d_o_n       : out std_logic;
-            pch_a_o_n       : out std_logic;
-            r_nw            : out std_logic
-        );
-end decoder;
-
-architecture rtl of decoder is
-
-type dec_status is (reset0, reset1, reset2, reset3, reset4, reset5, fetch);
-
-signal cur_stat : dec_status;
-
-begin
-
-    main_p : process (set_clk, trig_clk, res_n)
-    begin
-        if (res_n'event and res_n = '0') then
-            cur_stat <= reset0;
-        else
-            if (set_clk'event and set_clk = '1') then
-                case cur_stat is
-                    when reset0 => 
-                    when fetch => 
-                        pcl_a_o_n <= '0';
-                        pch_a_o_n <= '0';
-                        r_nw <= '1';
-                    when others => null;
-                end case;
-            end if;
-
-            if (trig_clk'event and trig_clk = '1') then
-                case cur_stat is
-                    when reset0 => 
-                        cur_stat <= reset1;
-                    when reset1 => 
-                        cur_stat <= reset2;
-                    when reset2 => 
-                        cur_stat <= reset3;
-                    when reset3 => 
-                        cur_stat <= reset4;
-                    when reset4 => 
-                        cur_stat <= reset5;
-                    when reset5 => 
-                        cur_stat <= fetch;
-                    when fetch => 
-                    when others => null;
-                end case;
-            end if;
-        end if;
-    end process;
-
-end rtl;
-

diff --git a/simulation/cpu/mos6502.vhd b/simulation/cpu/mos6502.vhd
index fdb547d..528c4e5 100644 (file)
--- a/simulation/cpu/mos6502.vhd
+++ b/simulation/cpu/mos6502.vhd
@@ -21,85 +21,22 @@ end mos6502;
 
 architecture rtl of mos6502 is
 
-    component pc
-        generic (
-                dsize : integer := 8;
-                reset_addr : integer := 0
-                );
-        port (  
-                trig_clk        : in std_logic;
-                res_n           : in std_logic;
-                dbus_in_n       : in std_logic;
-                dbus_out_n      : in std_logic;
-                abus_out_n      : in std_logic;
-                int_d_bus       : inout std_logic_vector (dsize - 1 downto 0);
-                int_a_bus       : out std_logic_vector (dsize - 1 downto 0)
-            );
-    end component;
-
-    component decoder
-        generic (dsize : integer := 8);
-        port (  set_clk         : in std_logic;
-                trig_clk        : in std_logic;
-                res_n           : in std_logic;
-                irq_n           : in std_logic;
-                nmi_n           : in std_logic;
-                rdy             : in std_logic;
-                instruction     : in std_logic_vector (dsize - 1 downto 0);
-                status_reg      : in std_logic_vector (dsize - 1 downto 0);
-                pcl_d_i_n       : out std_logic;
-                pcl_d_o_n       : out std_logic;
-                pcl_a_o_n       : out std_logic;
-                pch_d_i_n       : out std_logic;
-                pch_d_o_n       : out std_logic;
-                pch_a_o_n       : out std_logic;
-                r_nw            : out std_logic
-            );
-    end component;
-
     signal set_clk : std_logic;
     signal trigger_clk : std_logic;
 
-    signal pcl_d_in_n : std_logic;
-    signal pcl_d_out_n : std_logic;
-    signal pcl_a_out_n : std_logic;
-    signal pch_d_in_n : std_logic;
-    signal pch_d_out_n : std_logic;
-    signal pch_a_out_n : std_logic;
-
-    --internal bus (address hi/lo, data)
-    signal internal_abus_h : std_logic_vector (dsize - 1 downto 0);
-    signal internal_abus_l : std_logic_vector (dsize - 1 downto 0);
-    signal internal_dbus : std_logic_vector (dsize - 1 downto 0);
-
+    signal pc : std_logic_vector (asize - 1 downto 0);
     signal instruction : std_logic_vector (dsize - 1 downto 0);
     signal status_reg : std_logic_vector (dsize - 1 downto 0);
 begin
 
-    ---instances....
-    pc_l : pc generic map (dsize, 16#00#) 
-            port map(trigger_clk, rst_n, pcl_d_in_n, pcl_d_out_n, pcl_a_out_n, 
-                    internal_dbus, internal_abus_l);
-    pc_h : pc generic map (dsize, 16#80#) 
-            port map(trigger_clk, rst_n, pch_d_in_n, pch_d_out_n, pch_a_out_n, 
-                    internal_dbus, internal_abus_h);
-
-    dec_inst : decoder generic map (dsize) 
-            port map(set_clk, trigger_clk, rst_n, irq_n, nmi_n, 
-                    rdy, instruction, status_reg,
-                    pcl_d_in_n, pcl_d_out_n, pcl_a_out_n,
-                    pch_d_in_n, pch_d_out_n, pch_a_out_n,
-                    r_nw
-                    );
-
     -- clock generate.
     phi1 <= input_clk;
     phi2 <= not input_clk;
     set_clk <= input_clk;
     trigger_clk <= not input_clk;
 
-    addr(asize - 1 downto dsize) <= internal_abus_h;
-    addr(dsize - 1 downto 0) <= internal_abus_l;
+    --addr(asize - 1 downto dsize) <= internal_abus_h;
+    --addr(dsize - 1 downto 0) <= internal_abus_l;
 
     reset_p : process (rst_n)
     begin

diff --git a/simulation/cpu/pc.vhd b/simulation/cpu/pc.vhd
deleted file mode 100644 (file)
index 59cbb0a..0000000
--- a/simulation/cpu/pc.vhd
+++ /dev/null
@@ -1,42 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.conv_std_logic_vector;
-
-entity pc is 
-    generic (
-            dsize : integer := 8;
-            reset_addr : integer := 0
-            );
-    port (  
-            trig_clk        : in std_logic;
-            res_n           : in std_logic;
-            dbus_in_n       : in std_logic;
-            dbus_out_n      : in std_logic;
-            abus_out_n      : in std_logic;
-            int_d_bus       : inout std_logic_vector (dsize - 1 downto 0);
-            int_a_bus       : out std_logic_vector (dsize - 1 downto 0)
-        );
-end pc;
-
-architecture rtl of pc is
-
-signal val : std_logic_vector (dsize - 1 downto 0);
-
-begin
-    int_a_bus <= val when abus_out_n = '0' else
-                (others => 'Z');
-    int_d_bus <= val when (dbus_out_n = '0' and dbus_in_n /= '0') else
-                (others => 'Z');
-
-    set_p : process (trig_clk, res_n)
-    begin
-        if ( trig_clk'event and trig_clk = '1') then
-            if (dbus_in_n = '0') then
-                val <= int_d_bus;
-            end if;
-        elsif (res_n'event and res_n = '0') then
-            val <= conv_std_logic_vector(reset_addr, dsize);
-        end if;
-    end process;
-end rtl;
-