[mips][msa] Matheus Almeida pointed out a silly mistake in r188893. Fixed it.

I accidentally changed the encoding of the MSA registers to zero instead of 0
to 31. This change restores the encoding the registers had prior to r188893.

This didn't show up in the existing tests because direct-object emission isn't
implemented yet for MSA.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188896 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td
index f2e97b6..0e762f2 100644 (file)
--- a/lib/Target/Mips/MipsRegisterInfo.td
+++ b/lib/Target/Mips/MipsRegisterInfo.td
@@ -174,7 +174,7 @@ let Namespace = "Mips" in {
   /// Mips MSA registers
   /// MSA and FPU cannot both be present unless the FPU has 64-bit registers
   foreach I = 0-31 in
-  def W#I : AFPR128<0, "w"#I, [!cast<AFPR64>("D"#I#"_64")]>,
+  def W#I : AFPR128<I, "w"#I, [!cast<AFPR64>("D"#I#"_64")]>,
             DwarfRegNum<[!add(I, 32)]>;
 
   // Hi/Lo registers