rti ok. pc inc timing bug fix.

diff --git a/de0_cv_nes/dummy-ppu.vhd b/de0_cv_nes/dummy-ppu.vhd
index 921d0b8..410bd7b 100644 (file)
--- a/de0_cv_nes/dummy-ppu.vhd
+++ b/de0_cv_nes/dummy-ppu.vhd
@@ -71,7 +71,7 @@ begin
     --- initiate nmi.\r
     nmi_p: process\r
     constant nmi_wait     : time := 880us;\r
-    constant vblank_time     : time := 60 us;\r
+    constant vblank_time     : time := 1000 us;\r
     begin\r
         po_vblank_n <= '1';\r
         wait for nmi_wait;\r

diff --git a/de0_cv_nes/mos6502.vhd b/de0_cv_nes/mos6502.vhd
index 0119c12..37b7c88 100644 (file)
--- a/de0_cv_nes/mos6502.vhd
+++ b/de0_cv_nes/mos6502.vhd
@@ -1170,7 +1170,7 @@ end;
                     elsif (reg_sub_state = ST_SUB30) then\r
                         --update instruction register.\r
                         reg_inst    <= reg_d_in;\r
-                    elsif (reg_sub_state = ST_SUB70) then\r
+                    elsif (reg_sub_state = ST_SUB73) then\r
                         --pc move next.\r
                         pc_inc;\r
                     end if;\r
@@ -1201,6 +1201,7 @@ end;
                 reg_main_state = ST_A44_T1 or\r
                 reg_main_state = ST_A44_T2 or\r
                 reg_main_state = ST_A53_T1 or\r
+                reg_main_state = ST_A55_T1 or\r
                 reg_main_state = ST_A561_T1 or\r
                 reg_main_state = ST_A562_T1 or\r
                 reg_main_state = ST_A562_T2 or\r
@@ -1662,6 +1663,30 @@ end;
                 --vector high...\r
                 reg_addr    <= "1111111111111011";\r
                 reg_pc_h    <= reg_d_in;\r
+\r
+           --rti.\r
+            elsif (reg_main_state = ST_A55_T2) then\r
+                --sp out (discarded.)\r
+                reg_addr    <= "00000001" & reg_sp;\r
+            elsif (reg_main_state = ST_A55_T3) then\r
+                --pull status\r
+                reg_addr    <= "00000001" & reg_sp;\r
+            elsif (reg_main_state = ST_A55_T4) then\r
+                --pull pcl\r
+                if (reg_sub_state = ST_SUB00) then\r
+                    reg_addr    <= "00000001" & reg_sp;\r
+                elsif (reg_sub_state = ST_SUB70) then\r
+                    reg_pc_l    <= reg_d_in;\r
+                end if;\r
+            elsif (reg_main_state = ST_A55_T5) then\r
+                --pull pch\r
+                if (reg_sub_state = ST_SUB00) then\r
+                    reg_addr    <= "00000001" & reg_sp;\r
+                elsif (reg_sub_state = ST_SUB70) then\r
+                    reg_pc_h    <= reg_d_in;\r
+                end if;\r
+\r
+\r
             end if;--if (reg_main_state = ST_RS_T0) then\r
         end if;--if (pi_rst_n = '0') then\r
     end process;\r
@@ -1765,9 +1790,12 @@ end;
                     reg_sp <= reg_sp - 1;\r
                 end if;\r
             elsif (reg_main_state = ST_A52_T2 or\r
+                reg_main_state = ST_A55_T2 or\r
+                reg_main_state = ST_A55_T3 or\r
+                reg_main_state = ST_A55_T4 or\r
                 reg_main_state = ST_A57_T2 or\r
                 reg_main_state = ST_A57_T3) then\r
-                --pull, rts.\r
+                --pull, rts, rti.\r
                 if (reg_sub_state = ST_SUB70) then\r
                     reg_sp <= reg_sp + 1;\r
                 end if;\r
@@ -2297,6 +2325,14 @@ end;
                         set_condition_result(FL_V, '1');\r
                     end if;\r
                 end if;\r
+\r
+            elsif (reg_main_state = ST_A55_T3) then\r
+                --rti, pull status reg.\r
+                if (reg_sub_state = ST_SUB30) then\r
+                    reg_status <= reg_d_in;\r
+                end if;--if (reg_sub_state = ST_SUB30) then\r
+\r
+\r
             end if;--if (reg_main_state = ST_A21_T1 or...\r
         end if;--if (pi_rst_n = '0') then\r
     end process;\r