elsif (reg_sub_state = ST_SUB30) then\r
--update instruction register.\r
reg_inst <= reg_d_in;\r
- elsif (reg_sub_state = ST_SUB70) then\r
+ elsif (reg_sub_state = ST_SUB73) then\r
--pc move next.\r
pc_inc;\r
end if;\r
reg_main_state = ST_A44_T1 or\r
reg_main_state = ST_A44_T2 or\r
reg_main_state = ST_A53_T1 or\r
+ reg_main_state = ST_A55_T1 or\r
reg_main_state = ST_A561_T1 or\r
reg_main_state = ST_A562_T1 or\r
reg_main_state = ST_A562_T2 or\r
--vector high...\r
reg_addr <= "1111111111111011";\r
reg_pc_h <= reg_d_in;\r
+\r
+ --rti.\r
+ elsif (reg_main_state = ST_A55_T2) then\r
+ --sp out (discarded.)\r
+ reg_addr <= "00000001" & reg_sp;\r
+ elsif (reg_main_state = ST_A55_T3) then\r
+ --pull status\r
+ reg_addr <= "00000001" & reg_sp;\r
+ elsif (reg_main_state = ST_A55_T4) then\r
+ --pull pcl\r
+ if (reg_sub_state = ST_SUB00) then\r
+ reg_addr <= "00000001" & reg_sp;\r
+ elsif (reg_sub_state = ST_SUB70) then\r
+ reg_pc_l <= reg_d_in;\r
+ end if;\r
+ elsif (reg_main_state = ST_A55_T5) then\r
+ --pull pch\r
+ if (reg_sub_state = ST_SUB00) then\r
+ reg_addr <= "00000001" & reg_sp;\r
+ elsif (reg_sub_state = ST_SUB70) then\r
+ reg_pc_h <= reg_d_in;\r
+ end if;\r
+\r
+\r
end if;--if (reg_main_state = ST_RS_T0) then\r
end if;--if (pi_rst_n = '0') then\r
end process;\r
reg_sp <= reg_sp - 1;\r
end if;\r
elsif (reg_main_state = ST_A52_T2 or\r
+ reg_main_state = ST_A55_T2 or\r
+ reg_main_state = ST_A55_T3 or\r
+ reg_main_state = ST_A55_T4 or\r
reg_main_state = ST_A57_T2 or\r
reg_main_state = ST_A57_T3) then\r
- --pull, rts.\r
+ --pull, rts, rti.\r
if (reg_sub_state = ST_SUB70) then\r
reg_sp <= reg_sp + 1;\r
end if;\r
set_condition_result(FL_V, '1');\r
end if;\r
end if;\r
+\r
+ elsif (reg_main_state = ST_A55_T3) then\r
+ --rti, pull status reg.\r
+ if (reg_sub_state = ST_SUB30) then\r
+ reg_status <= reg_d_in;\r
+ end if;--if (reg_sub_state = ST_SUB30) then\r
+\r
+\r
end if;--if (reg_main_state = ST_A21_T1 or...\r
end if;--if (pi_rst_n = '0') then\r
end process;\r