// fb<cond> %fcc0, $imm
def : InstAlias<!strconcat(!strconcat("fb", cond), " %fcc0, $imm"),
- (BPFCC brtarget:$imm, condVal)>, Requires<[HasV9]>;
+ (BPFCC brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
// fb<cond>,pt %fcc0, $imm
def : InstAlias<!strconcat(!strconcat("fb", cond), ",pt %fcc0, $imm"),
- (BPFCC brtarget:$imm, condVal)>, Requires<[HasV9]>;
+ (BPFCC brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
// fb<cond>,a %fcc0, $imm
def : InstAlias<!strconcat(!strconcat("fb", cond), ",a %fcc0, $imm"),
- (BPFCCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
+ (BPFCCA brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
// fb<cond>,a,pt %fcc0, $imm
def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pt %fcc0, $imm"),
- (BPFCCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
+ (BPFCCA brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
// fb<cond>,pn %fcc0, $imm
def : InstAlias<!strconcat(!strconcat("fb", cond), ",pn %fcc0, $imm"),
- (BPFCCNT brtarget:$imm, condVal)>, Requires<[HasV9]>;
+ (BPFCCNT brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
// fb<cond>,a,pn %fcc0, $imm
def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pn %fcc0, $imm"),
- (BPFCCANT brtarget:$imm, condVal)>, Requires<[HasV9]>;
+ (BPFCCANT brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
defm : cond_mov_alias<cond, condVal, " %fcc0",
MOVFCCrr, MOVFCCri,
string asmstr, list<dag> pattern>
: F4<op3, outs, ins, asmstr, pattern> {
- bits<3> cc;
+ bit intcc;
+ bits<2> cc;
bits<4> cond;
bits<5> rs2;
let Inst{4-0} = rs2;
- let Inst{11} = cc{0};
- let Inst{12} = cc{1};
+ let Inst{12-11} = cc;
let Inst{13} = 0;
let Inst{17-14} = cond;
- let Inst{18} = cc{2};
+ let Inst{18} = intcc;
}
class F4_2<bits<6> op3, dag outs, dag ins,
string asmstr, list<dag> pattern>
: F4<op3, outs, ins, asmstr, pattern> {
- bits<3> cc;
+ bit intcc;
+ bits<2> cc;
bits<4> cond;
bits<11> simm11;
let Inst{10-0} = simm11;
- let Inst{11} = cc{0};
- let Inst{12} = cc{1};
+ let Inst{12-11} = cc;
let Inst{13} = 1;
let Inst{17-14} = cond;
- let Inst{18} = cc{2};
+ let Inst{18} = intcc;
}
class F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins,
string asmstr, list<dag> pattern>
: F4<op3, outs, ins, asmstr, pattern> {
bits<4> cond;
- bits<3> opf_cc;
+ bit intcc;
+ bits<2> opf_cc;
bits<5> rs2;
let Inst{18} = 0;
let Inst{17-14} = cond;
- let Inst{13-11} = opf_cc;
+ let Inst{13} = intcc;
+ let Inst{12-11} = opf_cc;
let Inst{10-5} = opf_low;
let Inst{4-0} = rs2;
}
// Conditional branch class on %fcc0-%fcc3 with predication:
multiclass FPredBranch {
- def CC : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
- "fb$cond %fcc0, $imm19", []>;
- def CCA : F2_3<0b101, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
- "fb$cond,a %fcc0, $imm19", []>;
- def CCNT : F2_3<0b101, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
- "fb$cond,pn %fcc0, $imm19", []>;
- def CCANT : F2_3<0b101, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
- "fb$cond,a,pn %fcc0, $imm19", []>;
+ def CC : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
+ FCCRegs:$cc),
+ "fb$cond $cc, $imm19", []>;
+ def CCA : F2_3<0b101, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
+ FCCRegs:$cc),
+ "fb$cond,a $cc, $imm19", []>;
+ def CCNT : F2_3<0b101, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
+ FCCRegs:$cc),
+ "fb$cond,pn $cc, $imm19", []>;
+ def CCANT : F2_3<0b101, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
+ FCCRegs:$cc),
+ "fb$cond,a,pn $cc, $imm19", []>;
}
} // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
[(SPbrfcc bb:$imm22, imm:$cond)]>;
def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
"fb$cond,a $imm22", []>;
-
- let Predicates = [HasV9], cc = 0b00 in
- defm BPF : FPredBranch;
}
+let Predicates = [HasV9] in
+ defm BPF : FPredBranch;
+
+
// Section B.24 - Call and Link Instruction, p. 125
// This is the only Format 1 instruction
let Uses = [O6],
// V9 Conditional Moves.
let Predicates = [HasV9], Constraints = "$f = $rd" in {
// Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
- let Uses = [ICC], cc = 0b100 in {
+ let Uses = [ICC], intcc = 1, cc = 0b00 in {
def MOVICCrr
: F4_1<0b101100, (outs IntRegs:$rd),
(ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
(SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>;
}
- let Uses = [FCC0], cc = 0b000 in {
+ let Uses = [FCC0], intcc = 0, cc = 0b00 in {
def MOVFCCrr
: F4_1<0b101100, (outs IntRegs:$rd),
(ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
(SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>;
}
- let Uses = [ICC], opf_cc = 0b100 in {
+ let Uses = [ICC], intcc = 1, opf_cc = 0b00 in {
def FMOVS_ICC
: F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
(ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
Requires<[HasHardQuad]>;
}
- let Uses = [FCC0], opf_cc = 0b000 in {
+ let Uses = [FCC0], intcc = 0, opf_cc = 0b00 in {
def FMOVS_FCC
: F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
(ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
"fcmpq $rd, $rs1, $rs2", []>,
Requires<[HasHardQuad]>;
-
// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
// the top 32-bits before using it. To do this clearing, we use a SRLri X,0.
let rs1 = 0 in