radeonsi: use DRAW_(INDEX_)INDIRECT_MULTI on Polaris

The non-MULTI variants will be removed in Polaris firmware.

Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 2aa0485902cdb4cd02b72627a760b00e71bffecf)

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 788869e..983d90b 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -593,11 +593,24 @@ static void si_emit_draw_packets(struct si_context *sctx,
                        radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
                        radeon_emit(cs, index_max_size);
 
-                       radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_INDIRECT, 3, render_cond_bit));
-                       radeon_emit(cs, info->indirect_offset);
-                       radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
-                       radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
-                       radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
+                       if (sctx->b.family < CHIP_POLARIS10) {
+                               radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_INDIRECT, 3, render_cond_bit));
+                               radeon_emit(cs, info->indirect_offset);
+                               radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
+                               radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
+                               radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
+                       } else {
+                               radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_INDIRECT_MULTI, 8, render_cond_bit));
+                               radeon_emit(cs, info->indirect_offset);
+                               radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
+                               radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
+                               radeon_emit(cs, 0); /* draw_index */
+                               radeon_emit(cs, 1); /* count */
+                               radeon_emit(cs, 0); /* count_addr -- disabled */
+                               radeon_emit(cs, 0);
+                               radeon_emit(cs, 16); /* stride */
+                               radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
+                       }
                } else {
                        index_va += info->start * ib->index_size;
 
@@ -620,11 +633,24 @@ static void si_emit_draw_packets(struct si_context *sctx,
                        radeon_emit(cs, indirect_va);
                        radeon_emit(cs, indirect_va >> 32);
 
-                       radeon_emit(cs, PKT3(PKT3_DRAW_INDIRECT, 3, render_cond_bit));
-                       radeon_emit(cs, info->indirect_offset);
-                       radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
-                       radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
-                       radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX);
+                       if (sctx->b.family < CHIP_POLARIS10) {
+                               radeon_emit(cs, PKT3(PKT3_DRAW_INDIRECT, 3, render_cond_bit));
+                               radeon_emit(cs, info->indirect_offset);
+                               radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
+                               radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
+                               radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX);
+                       } else {
+                               radeon_emit(cs, PKT3(PKT3_DRAW_INDIRECT_MULTI, 8, render_cond_bit));
+                               radeon_emit(cs, info->indirect_offset);
+                               radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
+                               radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
+                               radeon_emit(cs, 0); /* draw_index */
+                               radeon_emit(cs, 1); /* count */
+                               radeon_emit(cs, 0); /* count_addr -- disabled */
+                               radeon_emit(cs, 0);
+                               radeon_emit(cs, 16); /* stride */
+                               radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX);
+                       }
                } else {
                        radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
                        radeon_emit(cs, info->count);