[X86][SSE] Add FPEXT vXf32 - vXf64 tests

Some basic subvector special cases based on PR36761

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337464 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/X86/vec_fpext.ll b/test/CodeGen/X86/vec_fpext.ll
index 6b546ea..6af04dd 100644 (file)
--- a/test/CodeGen/X86/vec_fpext.ll
+++ b/test/CodeGen/X86/vec_fpext.ll
@@ -1,10 +1,83 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.1 -show-mc-encoding | FileCheck %s --check-prefix=X32-SSE
-; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefix=X32-AVX
-; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx512vl -show-mc-encoding | FileCheck %s --check-prefix=X32-AVX512VL
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 -show-mc-encoding | FileCheck %s --check-prefix=X64-SSE
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefix=X64-AVX
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512vl -show-mc-encoding | FileCheck %s --check-prefix=X64-AVX512VL
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.1 -show-mc-encoding | FileCheck %s --check-prefixes=SSE,X32-SSE
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=AVX,X32-AVX
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=AVX512VL,X32-AVX512VL
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 -show-mc-encoding | FileCheck %s --check-prefixes=SSE,X64-SSE
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=AVX,X64-AVX
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=AVX512VL,X64-AVX512VL
+
+define <2 x double> @fpext_4f32_to_2f64(<4 x float> %a) {
+; SSE-LABEL: fpext_4f32_to_2f64:
+; SSE:       # %bb.0:
+; SSE-NEXT:    cvtps2pd %xmm0, %xmm0 # encoding: [0x0f,0x5a,0xc0]
+; SSE-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
+;
+; AVX-LABEL: fpext_4f32_to_2f64:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vcvtps2pd %xmm0, %ymm0 # encoding: [0xc5,0xfc,0x5a,0xc0]
+; AVX-NEXT:    # kill: def $xmm0 killed $xmm0 killed $ymm0
+; AVX-NEXT:    vzeroupper # encoding: [0xc5,0xf8,0x77]
+; AVX-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
+;
+; AVX512VL-LABEL: fpext_4f32_to_2f64:
+; AVX512VL:       # %bb.0:
+; AVX512VL-NEXT:    vcvtps2pd %xmm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfc,0x5a,0xc0]
+; AVX512VL-NEXT:    # kill: def $xmm0 killed $xmm0 killed $ymm0
+; AVX512VL-NEXT:    vzeroupper # encoding: [0xc5,0xf8,0x77]
+; AVX512VL-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
+  %cvt = fpext <4 x float> %a to <4 x double>
+  %shuf = shufflevector <4 x double> %cvt, <4 x double> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x double> %shuf
+}
+
+define <2 x double> @fpext_8f32_to_2f64(<8 x float> %a) {
+; SSE-LABEL: fpext_8f32_to_2f64:
+; SSE:       # %bb.0:
+; SSE-NEXT:    cvtps2pd %xmm0, %xmm0 # encoding: [0x0f,0x5a,0xc0]
+; SSE-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
+;
+; AVX-LABEL: fpext_8f32_to_2f64:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vcvtps2pd %xmm0, %ymm0 # encoding: [0xc5,0xfc,0x5a,0xc0]
+; AVX-NEXT:    # kill: def $xmm0 killed $xmm0 killed $ymm0
+; AVX-NEXT:    vzeroupper # encoding: [0xc5,0xf8,0x77]
+; AVX-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
+;
+; AVX512VL-LABEL: fpext_8f32_to_2f64:
+; AVX512VL:       # %bb.0:
+; AVX512VL-NEXT:    vcvtps2pd %ymm0, %zmm0 # encoding: [0x62,0xf1,0x7c,0x48,0x5a,0xc0]
+; AVX512VL-NEXT:    # kill: def $xmm0 killed $xmm0 killed $zmm0
+; AVX512VL-NEXT:    vzeroupper # encoding: [0xc5,0xf8,0x77]
+; AVX512VL-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
+  %cvt = fpext <8 x float> %a to <8 x double>
+  %shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x double> %shuf
+}
+
+define <4 x double> @fpext_8f32_to_4f64(<8 x float> %a) {
+; SSE-LABEL: fpext_8f32_to_4f64:
+; SSE:       # %bb.0:
+; SSE-NEXT:    cvtps2pd %xmm0, %xmm2 # encoding: [0x0f,0x5a,0xd0]
+; SSE-NEXT:    movhlps %xmm0, %xmm0 # encoding: [0x0f,0x12,0xc0]
+; SSE-NEXT:    # xmm0 = xmm0[1,1]
+; SSE-NEXT:    cvtps2pd %xmm0, %xmm1 # encoding: [0x0f,0x5a,0xc8]
+; SSE-NEXT:    movaps %xmm2, %xmm0 # encoding: [0x0f,0x28,0xc2]
+; SSE-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
+;
+; AVX-LABEL: fpext_8f32_to_4f64:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vcvtps2pd %xmm0, %ymm0 # encoding: [0xc5,0xfc,0x5a,0xc0]
+; AVX-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
+;
+; AVX512VL-LABEL: fpext_8f32_to_4f64:
+; AVX512VL:       # %bb.0:
+; AVX512VL-NEXT:    vcvtps2pd %ymm0, %zmm0 # encoding: [0x62,0xf1,0x7c,0x48,0x5a,0xc0]
+; AVX512VL-NEXT:    # kill: def $ymm0 killed $ymm0 killed $zmm0
+; AVX512VL-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
+  %cvt = fpext <8 x float> %a to <8 x double>
+  %shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  ret <4 x double> %shuf
+}
 
 ; PR11674
 define void @fpext_frommem(<2 x float>* %in, <2 x double>* %out) {