This adds the CSDB instruction, which is a new barrier instruction
described by the whitepaper at [1].
This is in encoding space which was previously executed as a NOP, so it is
available for all targets that have the relevant NOP encoding space. This
matches the binutils behaviour for these instructions [2][3].
[1] https://developer.arm.com/support/security-update
[2] https://sourceware.org/ml/binutils/2018-01/msg00116.html
[3] https://sourceware.org/ml/binutils/2018-01/msg00120.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324324
91177308-0d34-0410-b5e6-
96231b3b80d8
def : InstAlias<"sev", (HINT 0b100)>;
def : InstAlias<"sevl", (HINT 0b101)>;
def : InstAlias<"esb", (HINT 0b10000)>, Requires<[HasRAS]>;
+def : InstAlias<"csdb", (HINT 20)>;
// v8.2a Statistical Profiling extension
def : InstAlias<"psb $op", (HINT psbhint_op:$op)>, Requires<[HasSPE]>;
def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>;
def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
def : InstAlias<"esb$p", (HINT 16, pred:$p)>, Requires<[IsARM, HasRAS]>;
+def : InstAlias<"csdb$p", (HINT 20, pred:$p)>, Requires<[IsARM, HasV6K]>;
def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
"\t$Rd, $Rn, $Rm",
def : t2InstAlias<"esb$p", (t2HINT 16, pred:$p), 0> {
let Predicates = [IsThumb2, HasRAS];
}
+def : t2InstAlias<"csdb$p.w", (t2HINT 20, pred:$p), 0>;
+def : t2InstAlias<"csdb$p", (t2HINT 20, pred:$p), 1>;
def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt",
[(int_arm_dbg imm0_15:$opt)]> {
break;
}
case ARM::HINT:
- case ARM::t2HINT:
- if (hasRAS()) {
- // ESB is not predicable (pred must be AL)
- unsigned Imm8 = Inst.getOperand(0).getImm();
- unsigned Pred = Inst.getOperand(1).getImm();
- if (Imm8 == 0x10 && Pred != ARMCC::AL)
- return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not "
- "predicable, but condition "
- "code specified");
- }
- // Without the RAS extension, this behaves as any other unallocated hint.
+ case ARM::t2HINT: {
+ unsigned Imm8 = Inst.getOperand(0).getImm();
+ unsigned Pred = Inst.getOperand(1).getImm();
+ // ESB is not predicable (pred must be AL). Without the RAS extension, this
+ // behaves as any other unallocated hint.
+ if (Imm8 == 0x10 && Pred != ARMCC::AL && hasRAS())
+ return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not "
+ "predicable, but condition "
+ "code specified");
+ if (Imm8 == 0x14 && Pred != ARMCC::AL)
+ return Error(Operands[1]->getStartLoc(), "instruction 'csdb' is not "
+ "predicable, but condition "
+ "code specified");
break;
}
+ }
return false;
}
--- /dev/null
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s
+
+ csdb
+// CHECK: csdb // encoding: [0x9f,0x22,0x03,0xd5]
--- /dev/null
+// RUN: not llvm-mc -triple armv8a-none-eabi %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple thumbv8a-none-eabi %s 2>&1 | FileCheck %s
+
+ it eq
+ csdbeq
+// CHECK: error: instruction 'csdb' is not predicable, but condition code specified
--- /dev/null
+@ RUN: llvm-mc -triple armv8a-none-eabi -show-encoding %s | FileCheck %s --check-prefix=ARM
+@ RUN: llvm-mc -triple thumbv8a-none-eabi -show-encoding %s | FileCheck %s --check-prefix=THUMB
+@ RUN: not llvm-mc -triple thumbv6m-none-eabi -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+ csdb
+@ ARM: csdb @ encoding: [0x14,0xf0,0x20,0xe3]
+@ THUMB: csdb @ encoding: [0xaf,0xf3,0x14,0x80]
+@ ERROR: error: instruction requires: thumb2
--- /dev/null
+# RUN: llvm-mc -triple aarch64-none-linux-gnu --disassemble < %s | FileCheck %s
+
+[0x9f,0x22,0x03,0xd5]
+# CHECK: csdb
--- /dev/null
+# RUN: llvm-mc < %s -triple armv8a-none-eabi -disassemble | FileCheck %s
+
+[0x14,0xf0,0x20,0xe3]
+# CHECK: csdb
--- /dev/null
+# RUN: llvm-mc < %s -triple thumbv8a-none-eabi -disassemble | FileCheck %s
+
+[0xaf,0xf3,0x14,0x80]
+# CHECK: csdb