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mmc: rtsx: clarify DDR timing mode between SD-UHS and eMMC
author
Seungwon Jeon
<tgih.jun@samsung.com>
Fri, 14 Mar 2014 12:12:38 +0000
(21:12 +0900)
committer
Chris Ball
<chris@printf.net>
Sun, 20 Apr 2014 20:59:56 +0000
(16:59 -0400)
Added MMC_DDR52 as eMMC's DDR mode is distinguished from SD-UHS.
CC: Wei WANG <wei_wang@realsil.com.cn>
CC: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Chris Ball <chris@printf.net>
drivers/mmc/host/rtsx_pci_sdmmc.c
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diff --git
a/drivers/mmc/host/rtsx_pci_sdmmc.c
b/drivers/mmc/host/rtsx_pci_sdmmc.c
index
5fb994f
..
8c2dd30
100644
(file)
--- a/
drivers/mmc/host/rtsx_pci_sdmmc.c
+++ b/
drivers/mmc/host/rtsx_pci_sdmmc.c
@@
-1075,6
+1075,7
@@
static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
break;
+ case MMC_TIMING_MMC_DDR52:
case MMC_TIMING_UHS_DDR50:
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
0x0C | SD_ASYNC_FIFO_NOT_RST,
@@
-1155,6
+1156,7
@@
static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
host->vpclk = true;
host->double_clk = false;
break;
+ case MMC_TIMING_MMC_DDR52:
case MMC_TIMING_UHS_DDR50:
case MMC_TIMING_UHS_SDR25:
host->ssc_depth = RTSX_SSC_DEPTH_1M;