drm/i915: Limit VF cache invalidate workaround usage to gen9

It is unclear if this is even required on BXT.

v2: Make sure to set the default value to false. Uncertain how my compiler
doesn't complain with v1.

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1450374597-7021-1-git-send-email-benjamin.widawsky@intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 3aa6147..ca5c0e8 100644 (file)
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1698,7 +1698,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
        struct intel_ringbuffer *ringbuf = request->ringbuf;
        struct intel_engine_cs *ring = ringbuf->ring;
        u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
-       bool vf_flush_wa;
+       bool vf_flush_wa = false;
        u32 flags = 0;
        int ret;
 
@@ -1719,14 +1719,14 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
                flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
                flags |= PIPE_CONTROL_QW_WRITE;
                flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
-       }
 
-       /*
-        * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
-        * control.
-        */
-       vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 &&
-                     flags & PIPE_CONTROL_VF_CACHE_INVALIDATE;
+               /*
+                * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
+                * pipe control.
+                */
+               if (IS_GEN9(ring->dev))
+                       vf_flush_wa = true;
+       }
 
        ret = intel_logical_ring_begin(request, vf_flush_wa ? 12 : 6);
        if (ret)