gas/testsuite/:

	* gas/m68k/cpu32.[sd]: New test.
	* gas/m68k/all.exp: Run it.

opcodes/:
	* m68k-opc.c: Fix encoding of signed bit in the cpu32 tbls insns.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index f5cb698..d398506 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2007-01-04  Andreas Schwab  <schwab@suse.de>
+
+       * m68k-opc.c: Fix encoding of signed bit in the cpu32 tbls insns.
+
 2007-01-04  Julian Brown  <julian@codesourcery.com>
 
        * arm-dis.c (neon_opcode): Fix disassembly for vshl, vqshl, vrshl,

diff --git a/opcodes/m68k-opc.c b/opcodes/m68k-opc.c
index 2feafc1..51b62d4 100644 (file)
--- a/opcodes/m68k-opc.c
+++ b/opcodes/m68k-opc.c
@@ -2151,8 +2151,8 @@ const struct m68k_opcode m68k_opcodes[] =
      two(0177770,0107770), "DsD3D1", cpu32 }
 #define TBL(name1, name2, name3, s, r) \
   TBL1(name1, 4, s, r, 0), TBL1(name2, 4, s, r, 1), TBL1(name3, 4, s, r, 2)
-TBL("tblsb", "tblsw", "tblsl", 2, 1),
-TBL("tblsnb", "tblsnw", "tblsnl", 2, 0),
+TBL("tblsb", "tblsw", "tblsl", 1, 1),
+TBL("tblsnb", "tblsnw", "tblsnl", 1, 0),
 TBL("tblub", "tbluw", "tblul", 0, 1),
 TBL("tblunb", "tblunw", "tblunl", 0, 0),