- Added VConstant as an abstract version of ConstantVec.

- All abstrct vector nodes must have # of elements and element type as their
first two operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26432 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h
index a4e8854..7e3b168 100644 (file)
--- a/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -63,10 +63,10 @@ namespace ISD {
     AssertSext, AssertZext,
 
     // Various leaf nodes.
-    Constant, ConstantFP, STRING,
-    GlobalAddress, FrameIndex, ConstantPool,
-    BasicBlock, ExternalSymbol, VALUETYPE, CONDCODE, Register,
-    
+    STRING, BasicBlock, VALUETYPE, CONDCODE, Register,
+    Constant, ConstantFP,
+    GlobalAddress, FrameIndex, ConstantPool, ExternalSymbol,
+
     // ConstantVec works like Constant or ConstantFP, except that it is not a
     // leaf node.  All operands are either Constant or ConstantFP nodes.
     ConstantVec,
@@ -85,6 +85,11 @@ namespace ISD {
     TargetConstantPool,
     TargetExternalSymbol,
 
+    // Abstract version of ConstantVec with abstract Vector type. The first node
+    // is a constant element count, the second is a value type indicating the
+    // type of the elements.
+    VConstant,
+
     // CopyToReg - This node has three operands: a chain, a register number to
     // set to this value, and a value.  
     CopyToReg,
@@ -139,9 +144,9 @@ namespace ISD {
     // Simple abstract vector operators.  Unlike the integer and floating point
     // binary operators, these nodes also take two additional operands:
     // a constant element count, and a value type node indicating the type of
-    // the elements.  The order is op0, op1, count, type.  All vector opcodes,
-    // including VLOAD, must currently have count and type as their 3rd and 4th
-    // arguments.
+    // the elements.  The order is count, type, op0, op1.  All vector opcodes,
+    // including VLOAD and VConstant must currently have count and type as
+    // their 1st and 2nd arguments.
     VADD, VSUB, VMUL,
 
     // MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing
@@ -243,9 +248,9 @@ namespace ISD {
     // SRCVALUE node that provides alias analysis information.
     LOAD, STORE,
     
-    // Abstract vector version of LOAD.  VLOAD has a token chain as the first
-    // operand, followed by a pointer operand, a constant element count, a value
-    // type node indicating the type of the elements, and a SRCVALUE node.
+    // Abstract vector version of LOAD.  VLOAD has a constant element count as
+    // the first operand, followed by a value type node indicating the type of
+    // the elements, a token chain, a pointer operand, and a SRCVALUE node.
     VLOAD,
 
     // EXTLOAD, SEXTLOAD, ZEXTLOAD - These three operators all load a value from

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index af77194..1800a59 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1400,10 +1400,10 @@ SDOperand SelectionDAG::getVecLoad(unsigned Count, MVT::ValueType EVT,
   if (N) return SDOperand(N, 0);
   std::vector<SDOperand> Ops;
   Ops.reserve(5);
-  Ops.push_back(Chain);
-  Ops.push_back(Ptr);
   Ops.push_back(getConstant(Count, MVT::i32));
   Ops.push_back(getValueType(EVT));
+  Ops.push_back(Chain);
+  Ops.push_back(Ptr);
   Ops.push_back(SV);
   std::vector<MVT::ValueType> VTs;
   VTs.reserve(2);
@@ -2557,26 +2557,33 @@ const char *SDNode::getOperationName(const SelectionDAG *G) const {
   case ISD::PCMARKER:      return "PCMarker";
   case ISD::READCYCLECOUNTER: return "ReadCycleCounter";
   case ISD::SRCVALUE:      return "SrcValue";
-  case ISD::VALUETYPE:     return "ValueType";
-  case ISD::STRING:        return "String";
   case ISD::EntryToken:    return "EntryToken";
   case ISD::TokenFactor:   return "TokenFactor";
   case ISD::AssertSext:    return "AssertSext";
   case ISD::AssertZext:    return "AssertZext";
+
+  case ISD::STRING:        return "String";
+  case ISD::BasicBlock:    return "BasicBlock";
+  case ISD::VALUETYPE:     return "ValueType";
+  case ISD::Register:      return "Register";
+
   case ISD::Constant:      return "Constant";
-  case ISD::TargetConstant: return "TargetConstant";
   case ISD::ConstantFP:    return "ConstantFP";
-  case ISD::ConstantVec:   return "ConstantVec";
   case ISD::GlobalAddress: return "GlobalAddress";
-  case ISD::TargetGlobalAddress: return "TargetGlobalAddress";
   case ISD::FrameIndex:    return "FrameIndex";
-  case ISD::TargetFrameIndex: return "TargetFrameIndex";
-  case ISD::BasicBlock:    return "BasicBlock";
-  case ISD::Register:      return "Register";
-  case ISD::ExternalSymbol: return "ExternalSymbol";
-  case ISD::TargetExternalSymbol: return "TargetExternalSymbol";
   case ISD::ConstantPool:  return "ConstantPool";
+  case ISD::ExternalSymbol: return "ExternalSymbol";
+
+  case ISD::ConstantVec:   return "ConstantVec";
+  case ISD::TargetConstant: return "TargetConstant";
+  case ISD::TargetConstantFP:return "TargetConstantFP";
+  case ISD::TargetConstantVec:return "TargetConstantVec";
+  case ISD::TargetGlobalAddress: return "TargetGlobalAddress";
+  case ISD::TargetFrameIndex: return "TargetFrameIndex";
   case ISD::TargetConstantPool:  return "TargetConstantPool";
+  case ISD::TargetExternalSymbol: return "TargetExternalSymbol";
+  case ISD::VConstant:     return "VConstant";
+
   case ISD::CopyToReg:     return "CopyToReg";
   case ISD::CopyFromReg:   return "CopyFromReg";
   case ISD::UNDEF:         return "undef";