drm/i915: Add TigerLake bandwidth checking

Added bandwidth calculation algorithm and checks,
similar way as it was done for ICL, some constants
were corrected according to BSpec 53998.

v2: Start using same icl_get_bw_info function to avoid
    code duplication. Moved mpagesize to memory info
    related structure as it is now dependent on memory type.
    Fixed qi.t_bl field assignment.

v3: Removed mpagesize as unused. Duplicate code and redundant blankline
    fixed.

v4: Changed ordering of IS_GEN checks as agreed. Minor commit
    message fixes.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111600
Reviewed-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190920083754.5920-1-stanislav.lisovskiy@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 688858e..cd58e47 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -56,7 +56,10 @@ static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv,
        qi->num_channels = (val & 0xf0) >> 4;
        qi->num_points = (val & 0xf00) >> 8;
 
-       qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8;
+       if (IS_GEN(dev_priv, 12))
+               qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 16;
+       else if (IS_GEN(dev_priv, 11))
+               qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8;
 
        return 0;
 }
@@ -132,20 +135,25 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
 }
 
 struct intel_sa_info {
-       u8 deburst, mpagesize, deprogbwlimit, displayrtids;
+       u16 displayrtids;
+       u8 deburst, deprogbwlimit;
 };
 
 static const struct intel_sa_info icl_sa_info = {
        .deburst = 8,
-       .mpagesize = 16,
        .deprogbwlimit = 25, /* GB/s */
        .displayrtids = 128,
 };
 
-static int icl_get_bw_info(struct drm_i915_private *dev_priv)
+static const struct intel_sa_info tgl_sa_info = {
+       .deburst = 16,
+       .deprogbwlimit = 34, /* GB/s */
+       .displayrtids = 256,
+};
+
+static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
 {
        struct intel_qgv_info qi = {};
-       const struct intel_sa_info *sa = &icl_sa_info;
        bool is_y_tile = true; /* assume y tile may be used */
        int num_channels;
        int deinterleave;
@@ -233,14 +241,16 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
 
 void intel_bw_init_hw(struct drm_i915_private *dev_priv)
 {
-       if (IS_GEN(dev_priv, 11))
-               icl_get_bw_info(dev_priv);
+       if (IS_GEN(dev_priv, 12))
+               icl_get_bw_info(dev_priv, &tgl_sa_info);
+       else if (IS_GEN(dev_priv, 11))
+               icl_get_bw_info(dev_priv, &icl_sa_info);
 }
 
 static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
                                        int num_planes)
 {
-       if (IS_GEN(dev_priv, 11))
+       if (INTEL_GEN(dev_priv) >= 11)
                /*
                 * FIXME with SAGV disabled maybe we can assume
                 * point 1 will always be used? Seems to match