arm64: dts: mt8192: Add video-codec nodes

Add video-codec lat and core nodes for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230303013842.23259-4-allen-kh.cheng@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index d28f5b1..693c55c 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1641,6 +1641,65 @@
                        power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
                };
 
+               vcodec_dec: video-codec@16000000 {
+                       compatible = "mediatek,mt8192-vcodec-dec";
+                       reg = <0 0x16000000 0 0x1000>;
+                       mediatek,scp = <&scp>;
+                       iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges = <0 0 0 0x16000000 0 0x26000>;
+
+                       video-codec@10000 {
+                               compatible = "mediatek,mtk-vcodec-lat";
+                               reg = <0x0 0x10000 0 0x800>;
+                               interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
+                               iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
+                                        <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
+                                        <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
+                                        <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
+                                        <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
+                                        <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
+                                        <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
+                                        <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
+                               clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+                                        <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+                                        <&vdecsys_soc CLK_VDEC_SOC_LAT>,
+                                        <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+                                        <&topckgen CLK_TOP_MAINPLL_D4>;
+                               clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
+                               assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+                               assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+                               power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
+                       };
+
+                       video-codec@25000 {
+                               compatible = "mediatek,mtk-vcodec-core";
+                               reg = <0 0x25000 0 0x1000>;
+                               interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
+                               iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
+                                        <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
+                                        <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
+                                        <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
+                                        <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
+                                        <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
+                                        <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
+                                        <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
+                                        <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
+                                        <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
+                                        <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
+                               clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+                                        <&vdecsys CLK_VDEC_VDEC>,
+                                        <&vdecsys CLK_VDEC_LAT>,
+                                        <&vdecsys CLK_VDEC_LARB1>,
+                                        <&topckgen CLK_TOP_MAINPLL_D4>;
+                               clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
+                               assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+                               assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+                               power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
+                       };
+               };
+
                larb5: larb@1600d000 {
                        compatible = "mediatek,mt8192-smi-larb";
                        reg = <0 0x1600d000 0 0x1000>;