set_irq(false);
set_drq(false);
if(data_queue != NULL) data_queue->clear();
+ is_dma = false;
}
-
+/*
#ifdef SCSI_HOST_WIDE
void SCSI_HOST::write_dma_io16(uint32_t addr, uint32_t data)
#else
#endif
return value;
}
-
-/*
+*/
void SCSI_HOST::write_dma_io8(uint32_t addr, uint32_t data)
{
- data_queue->write(data & 0xff);
+#if defined(USE_QUEUED_SCSI_TRANSFER)
+ if(!(cd_status) && !(msg_status) && (is_dma) && (req_status)) {
+ // Data IN/OUT
+ data_queue->write(data & 0xff);
+ return;
+ }
+#endif
+ write_signals(&outputs_dat, data);
+ #ifdef SCSI_HOST_AUTO_ACK
+ // set ack to clear req signal immediately
+ if((bsy_status) && !(io_status)) {
+ this->write_signal(SIG_SCSI_ACK, 1, 1);
+ }
+ #endif
}
void SCSI_HOST::write_dma_io16(uint32_t addr, uint32_t data)
{
write_dma_io8(addr, data);
return;
}
+#if defined(USE_QUEUED_SCSI_TRANSFER)
+ if(!(cd_status) && !(msg_status) && (is_dma) && (req_status)) {
+ // Data IN/OUT
#if !defined(SCSI_HOST_WIDE)
- data_queue->write(data & 0xff);
- data_queue->write((data >> 8) & 0xff);
+ data_queue->write(data & 0xff);
+ data_queue->write((data >> 8) & 0xff);
#else
- data_queue->write(data & 0xffff);
-#endif
+ data_queue->write(data & 0xffff);
+#endif
+ return;
+ }
+#endif
+ write_signals(&outputs_dat, data);
+ #ifdef SCSI_HOST_AUTO_ACK
+ // set ack to clear req signal immediately
+ if((bsy_status) && !(io_status)) {
+ this->write_signal(SIG_SCSI_ACK, 1, 1);
+ }
+ #endif
}
uint32_t SCSI_HOST::read_dma_io16(uint32_t addr)
{
return read_dma_io8(addr);
}
uint32_t val;
+#if defined(USE_QUEUED_SCSI_TRANSFER)
+ if(!(cd_status) && !(msg_status) && (is_dma) && (req_status)) {
+ // Data IN/OUT
#if !defined(SCSI_HOST_WIDE)
- val = data_queue->read() & 0xff;
- val = val << 8;
- val = val | (data_queue->read() & 0xff);
+ val = data_queue->read() & 0xff;
+ val = val << 8;
+ val = val | (data_queue->read() & 0xff);
#else
- val = data_queue->read() & 0xffff;
+ val = data_queue->read() & 0xffff;
+#endif
+ return val;
+ }
#endif
+ val = data_reg;
+ #ifdef SCSI_HOST_AUTO_ACK
+ // set ack to clear req signal immediately
+ if((bsy_status) && (io_status)) {
+ this->write_signal(SIG_SCSI_ACK, 1, 1);
+ }
+ #endif
return val;
}
uint32_t SCSI_HOST::read_dma_io8(uint32_t addr)
{
- uint32_t val = data_queue->read() & 0xff;
+ uint32_t val;
+#if defined(USE_QUEUED_SCSI_TRANSFER)
+ if(!(cd_status) && !(msg_status) && (is_dma) && (req_status)) {
+// if(!(data_queue->empty())) {
+ // Data IN/OUT
+ val = data_queue->read() & 0xff;
+ return val;
+ }
+#endif
+ val = data_reg;
+ #ifdef SCSI_HOST_AUTO_ACK
+ // set ack to clear req signal immediately
+ if((bsy_status) && (io_status)) {
+ this->write_signal(SIG_SCSI_ACK, 1, 1);
+ }
+ #endif
return val;
}
-*/
+
void SCSI_HOST::event_callback(int id, int err)
{
this->out_debug_log(_T("[SCSI_HOST] RST = %d\n"), (data & mask) ? 1 : 0);
#endif
write_signals(&outputs_rst, (data & mask) ? 0xffffffff : 0);
- if(data_queue != NULL) {
+ if((data_queue != NULL) && ((data & mask) != 0)) {
data_queue->clear();
}
break;
if(!prev_status && req_status) {
// L -> H
// if(bsy_status) {
- /*
- if(((cd_status) && !(msg_status) && (io_status)) ||
- (!(cd_status) && !(msg_status) && !(io_status))) { // STATUS or DATA_OUT
- #if defined(SCSI_HOST_WIDE)
- data_queue->write(data_reg & 0xffff);
- #else
- data_queue->write(data_reg & 0xff);
- #endif
- register_event(this, EVENT_DELAY_READ_ACK, 0.5, false, NULL);
- }
- */
if(!cd_status && !msg_status) {
// data phase
- #if 0
- if(is_16bit) {
- if((data_queue->count() & 1) == 0) {
- set_drq(true);
+
+#if defined(USE_QUEUED_SCSI_TRANSFER)
+ if((bsy_status) && (io_status) && (is_dma)) {
+ data_queue->write(data_reg);
+// out_debug_log(_T("READ DATA=%02X"), data_reg, data_queue->count());
+ #ifdef SCSI_HOST_AUTO_ACK
+ this->write_signal(SIG_SCSI_ACK, 1, 1);
+ #endif
+ }
+#endif
+
+ #if !defined(SCSI_HOST_WIDE) && defined(USE_QUEUED_SCSI_TRANSFER)
+ bool do_drq = false;
+ if((io_status)) {
+ // READ FROM TARGET
+ if(!(data_queue->empty())) {
+ do_drq = true;
}
} else {
- set_drq(true);
+ // WRITE TO TARGET
+ if((data_queue->empty())) {
+ do_drq = true;
+ }
}
+ if(do_drq) set_drq(true);
#else
set_drq(true);
#endif
access = true;
+#if defined(USE_QUEUED_SCSI_TRANSFER)
+ if((bsy_status) && !(io_status) && (is_dma)) {
+ if(!(data_queue->empty())) {
+ write_signals(&outputs_dat, data_queue->read());
+ #ifdef SCSI_HOST_AUTO_ACK
+ this->write_signal(SIG_SCSI_ACK, 1, 1);
+ #endif
+ }
+ }
+#endif
} else if(cd_status) {
// command/status/message phase
+ if(!(data_queue->empty())) data_queue->clear();
set_irq(true);
}
// }
- /*
- if(((cd_status) && !(msg_status) && !(io_status)) ||
- (!(cd_status) && !(msg_status) && (io_status))) { // COMMAND or DATA_IN
- uint32_t val;
- if(!(data_queue->empty())) {
- val = data_queue->read();
- data_reg = val;
- #if defined(SCSI_HOST_WIDE)
- val = val & 0xffff;
- #else
- val = val & 0xff;
- #endif
- write_signals(&outputs_dat, val);
- register_event(this, EVENT_DELAY_WRITE_ACK, 0.5, false, NULL);
- }
- }
- */
} else if(prev_status && !req_status) {
// H -> L
set_drq(false);
write_signals(&outputs_req, req_status ? 0xffffffff : 0);
}
break;
+ case SIG_SCSI_HOST_DMAE:
+ is_dma = ((data & mask) != 0) ? true : false;
+ break;
case SIG_SCSI_16BIT_BUS:
is_16bit = ((data & mask) != 0) ? true : false;
break;
if(!data_queue->process_state((void *)state_fio, loading)) {
return false;
}
+ state_fio->StateValue(is_dma);
return true;
}
//class VM;
class FIFO;
+#define SIG_SCSI_HOST_DMAE 1
class SCSI_HOST : public DEVICE
{
protected: // Make pcotected because TOWNS's DMAC may transfer 16bit around SCSI.
uint32_t bsy_status, cd_status, io_status, msg_status, req_status, ack_status;
bool access;
bool is_16bit;
+ bool is_dma;
virtual void __FASTCALL set_irq(bool value);
virtual void __FASTCALL set_drq(bool value);
virtual void initialize();
virtual void release();
virtual void event_callback(int id, int err);
-
+/*
#ifdef SCSI_HOST_WIDE
virtual void __FASTCALL write_dma_io16(uint32_t addr, uint32_t data);
virtual uint32_t __FASTCALL read_dma_io16(uint32_t addr);
virtual void __FASTCALL write_dma_io8(uint32_t addr, uint32_t data);
virtual uint32_t __FASTCALL read_dma_io8(uint32_t addr);
#endif
-/*
+*/
virtual void __FASTCALL write_dma_io8(uint32_t addr, uint32_t data);
virtual void __FASTCALL write_dma_io16(uint32_t addr, uint32_t data);
virtual uint32_t __FASTCALL read_dma_io8(uint32_t addr);
virtual uint32_t __FASTCALL read_dma_io16(uint32_t addr);
-*/
+
virtual void __FASTCALL write_signal(int id, uint32_t data, uint32_t mask);
virtual uint32_t __FASTCALL read_signal(int id);
virtual bool process_state(FILEIO* state_fio, bool loading);