Skl: Add the PCIIDs and initial driver-codec info for Skl

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit 7d3be309fed0330097426ffd5a055cb2db473236)

Conflicts:

	src/intel_driver.h

diff --git a/src/i965_device_info.c b/src/i965_device_info.c
index ee910a4..f39f2eb 100644 (file)
--- a/src/i965_device_info.c
+++ b/src/i965_device_info.c
@@ -306,6 +306,49 @@ static struct hw_codec_info chv_hw_codec_info = {
     },
 };
 
+/* TODO: Add the separate call back function for Gen9 */
+static struct hw_codec_info skl_hw_codec_info = {
+    .dec_hw_context_init = gen8_dec_hw_context_init,
+    .enc_hw_context_init = gen8_enc_hw_context_init,
+    .proc_hw_context_init = gen75_proc_context_init,
+    .render_init = gen8_render_init,
+    .post_processing_context_init = gen8_post_processing_context_init,
+
+    .max_width = 4096,
+    .max_height = 4096,
+    .min_linear_wpitch = 64,
+    .min_linear_hpitch = 16,
+
+    .h264_mvc_dec_profiles = (VA_PROFILE_MASK(H264StereoHigh) |
+                              VA_PROFILE_MASK(H264MultiviewHigh)),
+    .h264_dec_chroma_formats = EXTRA_H264_DEC_CHROMA_FORMATS,
+    .jpeg_dec_chroma_formats = EXTRA_JPEG_DEC_CHROMA_FORMATS,
+
+    .has_mpeg2_decoding = 1,
+    .has_mpeg2_encoding = 1,
+    .has_h264_decoding = 1,
+    .has_h264_encoding = 1,
+    .has_vc1_decoding = 1,
+    .has_jpeg_decoding = 1,
+    .has_vpp = 1,
+    .has_accelerated_getimage = 1,
+    .has_accelerated_putimage = 1,
+    .has_tiled_surface = 1,
+    .has_di_motion_adptive = 1,
+    .has_di_motion_compensated = 1,
+    .has_vp8_decoding = 1,
+    .has_h264_mvc_encoding = 1,
+
+    .num_filters = 5,
+    .filters = {
+        { VAProcFilterNoiseReduction, I965_RING_VEBOX },
+        { VAProcFilterDeinterlacing, I965_RING_VEBOX },
+        { VAProcFilterSharpening, I965_RING_NULL }, /* need to rebuild the shader for BDW */
+        { VAProcFilterColorBalance, I965_RING_VEBOX},
+        { VAProcFilterSkinToneEnhancement, I965_RING_VEBOX},
+    },
+};
+
 struct hw_codec_info *
 i965_get_codec_info(int devid)
 {
@@ -427,6 +470,13 @@ static const struct intel_device_info chv_device_info = {
     .is_cherryview = 1,
 };
 
+static const struct intel_device_info skl_device_info = {
+    .gen = 9,
+
+    .urb_size = 4096,
+    .max_wm_threads = 64,       /* per PSD */
+};
+
 const struct intel_device_info *
 i965_get_device_info(int devid)
 {

diff --git a/src/i965_pciids.h b/src/i965_pciids.h
index fc046d1..22b8215 100644 (file)
--- a/src/i965_pciids.h
+++ b/src/i965_pciids.h
@@ -133,3 +133,18 @@ CHIPSET(0x22B0, chv, chv,       "Intel(R) CherryView")
 CHIPSET(0x22B1, chv, chv,       "Intel(R) CherryView")
 CHIPSET(0x22B2, chv, chv,       "Intel(R) CherryView")
 CHIPSET(0x22B3, chv, chv,       "Intel(R) CherryView")
+CHIPSET(0x1902, skl, skl,       "Intel(R) Skylake")
+CHIPSET(0x1906, skl, skl,       "Intel(R) Skylake")
+CHIPSET(0x190E, skl, skl,       "Intel(R) Skylake")
+CHIPSET(0x1912, skl, skl,       "Intel(R) Skylake")
+CHIPSET(0x1913, skl, skl,       "Intel(R) Skylake")
+CHIPSET(0x1915, skl, skl,       "Intel(R) Skylake")
+CHIPSET(0x1916, skl, skl,       "Intel(R) Skylake")
+CHIPSET(0x1917, skl, skl,       "Intel(R) Skylake")
+CHIPSET(0x191B, skl, skl,       "Intel(R) Skylake")
+CHIPSET(0x191E, skl, skl,       "Intel(R) Skylake")
+CHIPSET(0x1921, skl, skl,       "Intel(R) Skylake")
+CHIPSET(0x1926, skl, skl,       "Intel(R) Skylake")
+CHIPSET(0x192B, skl, skl,       "Intel(R) Skylake")
+CHIPSET(0x193A, skl, skl,       "Intel(R) Skylake")
+CHIPSET(0x193B, skl, skl,       "Intel(R) Skylake")

diff --git a/src/intel_driver.h b/src/intel_driver.h
index 432a0d9..8ec7f58 100644 (file)
--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -192,4 +192,6 @@ struct intel_region
 #define IS_CHERRYVIEW(device_info)      (device_info->is_cherryview)
 #define IS_GEN8(device_info)            (device_info->gen == 8)
 
+#define IS_GEN9(device_info)            (device_info->gen == 9)
+
 #endif /* _INTEL_DRIVER_H_ */