rtw89: refine DIG feature to support 160M and CCK PD

DIG, which is short for dynamic initial gain, is used to adjust gain to get
good RX performance. CCK PD feature, a mechanism that adjusts 802.11b CCK
packet detection(PD) power threshold based on environment noisy level in
order to avoid false alarm. Also, refine related variable naming.

Signed-off-by: Johnson Lin <johnson.lin@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220121075555.12457-1-pkshih@realtek.com

diff --git a/drivers/net/wireless/realtek/rtw89/core.c b/drivers/net/wireless/realtek/rtw89/core.c
index b105e59..490f5d8 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/core.c
+++ b/drivers/net/wireless/realtek/rtw89/core.c
@@ -2563,6 +2563,13 @@ static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev)
        rtwdev->hal.cv = cv;
 }
 
+static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev)
+{
+       rtwdev->hal.support_cckpd =
+               !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) &&
+               !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV);
+}
+
 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev)
 {
        int ret;
@@ -2583,6 +2590,8 @@ static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev)
        if (ret)
                return ret;
 
+       rtw89_core_setup_phycap(rtwdev);
+
        rtw89_mac_pwr_off(rtwdev);
 
        return 0;

diff --git a/drivers/net/wireless/realtek/rtw89/core.h b/drivers/net/wireless/realtek/rtw89/core.h
index b7e26cf..cb71dfc 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/core.h
+++ b/drivers/net/wireless/realtek/rtw89/core.h
@@ -2378,6 +2378,7 @@ struct rtw89_hal {
        u32 antenna_rx;
        u8 tx_nss;
        u8 rx_nss;
+       bool support_cckpd;
 };
 
 #define RTW89_MAX_MAC_ID_NUM 128

diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c
index f807c18..1858126 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/phy.c
+++ b/drivers/net/wireless/realtek/rtw89/phy.c
@@ -2855,7 +2855,9 @@ static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi,
        enum rtw89_bandwidth cbw = rtwdev->hal.current_band_width;
        struct rtw89_dig_info *dig = &rtwdev->dig;
        u8 final_rssi = 0, under_region = dig->pd_low_th_ofst;
-       u32 val = 0;
+       u8 ofdm_cca_th;
+       s8 cck_cca_th;
+       u32 pd_val = 0;
 
        under_region += PD_TH_SB_FLTR_CMP_VAL;
 
@@ -2866,6 +2868,9 @@ static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi,
        case RTW89_CHANNEL_WIDTH_80:
                under_region += PD_TH_BW80_CMP_VAL;
                break;
+       case RTW89_CHANNEL_WIDTH_160:
+               under_region += PD_TH_BW160_CMP_VAL;
+               break;
        case RTW89_CHANNEL_WIDTH_20:
                fallthrough;
        default:
@@ -2876,23 +2881,38 @@ static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi,
        dig->dyn_pd_th_max = dig->igi_rssi;
 
        final_rssi = min_t(u8, rssi, dig->igi_rssi);
-       final_rssi = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region,
-                            PD_TH_MAX_RSSI + under_region);
+       ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region,
+                             PD_TH_MAX_RSSI + under_region);
 
        if (enable) {
-               val = (final_rssi - under_region - PD_TH_MIN_RSSI) >> 1;
+               pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1;
                rtw89_debug(rtwdev, RTW89_DBG_DIG,
-                           "dyn_max=%d, final_rssi=%d, total=%d, PD_low=%d\n",
-                           dig->igi_rssi, final_rssi, under_region, val);
+                           "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n",
+                           final_rssi, ofdm_cca_th, under_region, pd_val);
        } else {
                rtw89_debug(rtwdev, RTW89_DBG_DIG,
                            "Dynamic PD th disabled, Set PD_low_bd=0\n");
        }
 
        rtw89_phy_write32_mask(rtwdev, R_SEG0R_PD, B_SEG0R_PD_LOWER_BOUND_MSK,
-                              val);
+                              pd_val);
        rtw89_phy_write32_mask(rtwdev, R_SEG0R_PD,
                               B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, enable);
+
+       if (!rtwdev->hal.support_cckpd)
+               return;
+
+       cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI);
+       pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX);
+
+       rtw89_debug(rtwdev, RTW89_DBG_DIG,
+                   "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n",
+                   final_rssi, cck_cca_th, under_region, pd_val);
+
+       rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_EN_V1,
+                              B_BMODE_PDTH_LIMIT_EN_MSK_V1, enable);
+       rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_V1,
+                              B_BMODE_PDTH_LOWER_BOUND_MSK_V1, pd_val);
 }
 
 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev)

diff --git a/drivers/net/wireless/realtek/rtw89/phy.h b/drivers/net/wireless/realtek/rtw89/phy.h
index 09580f1..2cb68f4 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/phy.h
+++ b/drivers/net/wireless/realtek/rtw89/phy.h
@@ -87,8 +87,11 @@
 #define RXB_IDX_MAX 31
 #define RXB_IDX_MIN 0
 
+#define IGI_RSSI_MAX 110
 #define PD_TH_MAX_RSSI 70
 #define PD_TH_MIN_RSSI 8
+#define CCKPD_TH_MIN_RSSI (-18)
+#define PD_TH_BW160_CMP_VAL 9
 #define PD_TH_BW80_CMP_VAL 6
 #define PD_TH_BW40_CMP_VAL 3
 #define PD_TH_BW20_CMP_VAL 0

diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h
index 5e5cb0f..b39e531 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/reg.h
+++ b/drivers/net/wireless/realtek/rtw89/reg.h
@@ -1971,6 +1971,10 @@
 #define R_CHBW_MOD 0x4978
 #define B_CHBW_MOD_PRICH GENMASK(11, 8)
 #define B_CHBW_MOD_SBW GENMASK(13, 12)
+#define R_BMODE_PDTH_V1 0x4B64
+#define B_BMODE_PDTH_LOWER_BOUND_MSK_V1 GENMASK(31, 24)
+#define R_BMODE_PDTH_EN_V1 0x4B74
+#define B_BMODE_PDTH_LIMIT_EN_MSK_V1 BIT(30)
 #define R_CFO_COMP_SEG1_L 0x5384
 #define R_CFO_COMP_SEG1_H 0x5388
 #define R_CFO_COMP_SEG1_CTRL 0x538C