// FrameIndex for the alloca.
std::map<AllocaInst*, unsigned> AllocaMap;
- // A Reg to hold the base address used for global loads and stores, and a
- // flag to set whether or not we need to emit it for this function.
- unsigned GlobalBaseReg;
- bool GlobalBaseInitialized;
-
ISel(TargetMachine &tm) : TM(reinterpret_cast<PPC64TargetMachine&>(tm)),
F(0), BB(0) {}
BB = &F->front();
- // Make sure we re-emit a set of the global base reg if necessary
- GlobalBaseInitialized = false;
-
// Copy incoming arguments off of the stack...
LoadArgumentsToVirtualRegs(Fn);
Value *Cond, Value *TrueVal, Value *FalseVal,
unsigned DestReg);
- /// copyGlobalBaseToRegister - Output the instructions required to put the
- /// base address to use for accessing globals into a register.
- ///
- void ISel::copyGlobalBaseToRegister(MachineBasicBlock *MBB,
- MachineBasicBlock::iterator IP,
- unsigned R);
-
/// copyConstantToRegister - Output the instructions required to put the
/// specified constant into the specified register.
///
}
-/// copyGlobalBaseToRegister - Output the instructions required to put the
-/// base address to use for accessing globals into a register.
-///
-void ISel::copyGlobalBaseToRegister(MachineBasicBlock *MBB,
- MachineBasicBlock::iterator IP,
- unsigned R) {
- if (!GlobalBaseInitialized) {
- // Insert the set of GlobalBaseReg into the first MBB of the function
- MachineBasicBlock &FirstMBB = F->front();
- MachineBasicBlock::iterator MBBI = FirstMBB.begin();
- GlobalBaseReg = makeAnotherReg(Type::IntTy);
- BuildMI(FirstMBB, MBBI, PPC::IMPLICIT_DEF, 0, PPC::LR);
- BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, GlobalBaseReg);
- GlobalBaseInitialized = true;
- }
- // Emit our copy of GlobalBaseReg to the destination register in the
- // current MBB
- BuildMI(*MBB, IP, PPC::OR, 2, R).addReg(GlobalBaseReg)
- .addReg(GlobalBaseReg);
-}
-
/// copyConstantToRegister - Output the instructions required to put the
/// specified constant into the specified register.
///
unsigned CPI = CP->getConstantPoolIndex(C);
BuildMI(*MBB, IP, PPC::LD, 1, R)
.addReg(PPC::R2).addConstantPoolIndex(CPI);
+ return;
}
assert(Class <= cInt && "Type not handled yet!");
/// emitUCOM - emits an unordered FP compare.
void ISel::emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
- unsigned LHS, unsigned RHS) {
+ unsigned LHS, unsigned RHS) {
BuildMI(*MBB, IP, PPC::FCMPU, 2, PPC::CR0).addReg(LHS).addReg(RHS);
}
// pass the float in an int. Otherwise, put it on the stack.
if (isVarArg) {
BuildMI(BB, PPC::STFS, 3).addReg(ArgReg).addSImm(ArgOffset)
- .addReg(PPC::R1);
+ .addReg(PPC::R1);
if (GPR_remaining > 0) {
BuildMI(BB, PPC::LWZ, 2, GPR[GPR_idx])
.addSImm(ArgOffset).addReg(ArgReg);
// registers and emit the appropriate opcode.
unsigned Op0r = getReg(Op0, MBB, IP);
unsigned Op1r = getReg(Op1, MBB, IP);
-
unsigned Opcode = OpcodeTab[OperatorClass];
BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
- return;
}
// ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
}
}
} else { // The shift amount is non-constant.
- unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
+ unsigned ShiftAmountReg = getReg(ShiftAmount, MBB, IP);
if (isLeftShift) {
BuildMI(*MBB, IP, PPC::SLW, 2, DestReg).addReg(SrcReg)
// PhiMBB:
// DestReg = phi [ IntTmp, OldMBB ], [ XorReg, XorMBB ]
BB = PhiMBB;
- BuildMI(BB, PPC::PHI, 2, DestReg).addReg(IntTmp).addMBB(OldMBB)
+ BuildMI(BB, PPC::PHI, 4, DestReg).addReg(IntTmp).addMBB(OldMBB)
.addReg(XorReg).addMBB(XorMBB);
}
}
// sbyte -1 -> ubyte 0xFFFFFFFF
BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
break;
- case cLong:
- ++SrcReg;
- // Fall through
case cInt:
+ case cLong:
if (DestClass == cInt)
BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
else