return phb;
}
-int chsc_sei_nt2_get_event(void *res)
+int pci_chsc_sei_nt2_get_event(void *res)
{
ChscSeiNt2Res *nt2_res = (ChscSeiNt2Res *)res;
PciCcdfAvail *accdf;
return rc;
}
-int chsc_sei_nt2_have_event(void)
+int pci_chsc_sei_nt2_have_event(void)
{
S390pciState *s = s390_get_phb();
} S390pciState;
S390pciState *s390_get_phb(void);
-int chsc_sei_nt2_get_event(void *res);
-int chsc_sei_nt2_have_event(void);
+int pci_chsc_sei_nt2_get_event(void *res);
+int pci_chsc_sei_nt2_have_event(void);
void s390_pci_sclp_configure(SCCB *sccb);
void s390_pci_sclp_deconfigure(SCCB *sccb);
void s390_pci_iommu_enable(S390PCIIOMMU *iommu);
#include "s390-pci-bus.h"
/* target/s390x/ioinst.c */
-int chsc_sei_nt2_get_event(void *res)
+int pci_chsc_sei_nt2_get_event(void *res)
{
return 1;
}
-int chsc_sei_nt2_have_event(void)
+int pci_chsc_sei_nt2_have_event(void)
{
return 0;
}
return 0;
}
+static int chsc_sei_nt2_get_event(void *res)
+{
+ if (s390_has_feat(S390_FEAT_ZPCI)) {
+ return pci_chsc_sei_nt2_get_event(res);
+ }
+ return 1;
+}
+
+static int chsc_sei_nt2_have_event(void)
+{
+ if (s390_has_feat(S390_FEAT_ZPCI)) {
+ return pci_chsc_sei_nt2_have_event();
+ }
+ return 0;
+}
+
#define CHSC_SEI_NT0 (1ULL << 63)
#define CHSC_SEI_NT2 (1ULL << 61)
static void ioinst_handle_chsc_sei(ChscReq *req, ChscResp *res)