program counter added.

diff --git a/simulation/cpu/Makefile b/simulation/cpu/Makefile
index 179cac1..68e056f 100644 (file)
--- a/simulation/cpu/Makefile
+++ b/simulation/cpu/Makefile
@@ -1,5 +1,7 @@
 
-MODULES=cpu_reg.vhd mos6502.vhd data_latch.vhd #cpu_timing.vhd 
+MODULES=pc.vhd data_latch.vhd \
+               mos6502.vhd 
+               #cpu_timing.vhd 
 
 WORKDIR=../work
 

diff --git a/simulation/cpu/cpu_reg.vhd b/simulation/cpu/cpu_reg.vhd
deleted file mode 100644 (file)
index a18973b..0000000
--- a/simulation/cpu/cpu_reg.vhd
+++ /dev/null
@@ -1,23 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity cpu_reg is 
-    generic (dsize : integer := 8);
-    port (  clk, en     : in std_logic;
-            d           : in std_logic_vector (dsize - 1 downto 0);
-            q           : out std_logic_vector (dsize - 1 downto 0)
-        );
-end cpu_reg;
-
-architecture rtl of cpu_reg is
-begin
-    p : process (clk)
-    begin
-    if (clk'event and clk = '1') then
-        if (en = '1') then
-            q <= d;
-        end if;
-    end if;
-    end process;
-end rtl;
-

diff --git a/simulation/cpu/mos6502.vhd b/simulation/cpu/mos6502.vhd
index da98f20..85a323c 100644 (file)
--- a/simulation/cpu/mos6502.vhd
+++ b/simulation/cpu/mos6502.vhd
@@ -22,22 +22,31 @@ end mos6502;
 
 architecture rtl of mos6502 is
 
-    component cpu_reg
+    component pc
         generic (dsize : integer := 8);
-        port (  clk, en     : in std_logic;
-                d           : in std_logic_vector (dsize - 1 downto 0);
-                q           : out std_logic_vector (dsize - 1 downto 0)
+        port (  trig_clk    : in std_logic;
+                dbus_in_n       : in std_logic;
+                dbus_out_n      : in std_logic;
+                abus_out_n      : in std_logic;
+                int_d_bus       : inout std_logic_vector (dsize - 1 downto 0);
+                int_a_bus       : out std_logic_vector (dsize - 1 downto 0)
             );
     end component;
 
     signal trigger_clk : std_logic;
-    signal pc_l_en : std_logic;
+    signal pc_d_in_n : std_logic;
+    signal pc_d_out_n : std_logic;
+    signal pc_a_out_n : std_logic;
+
+    signal internal_abus_h : std_logic_vector (dsize - 1 downto 0);
+    signal internal_abus_l : std_logic_vector (dsize - 1 downto 0);
     signal internal_dbus : std_logic_vector (dsize - 1 downto 0);
 
 begin
 
-    pc_l : cpu_reg generic map (dsize) 
-            port map(trigger_clk, pc_l_en, internal_dbus, internal_dbus);
+    pc_l : pc generic map (dsize) 
+            port map(trigger_clk, pc_d_in_n, pc_d_out_n, pc_a_out_n, 
+                    internal_dbus, internal_abus_l);
 
     -- clock generate.
     phi1 <= input_clk;

diff --git a/simulation/cpu/pc.vhd b/simulation/cpu/pc.vhd
new file mode 100644 (file)
index 0000000..94d89d5
--- /dev/null
+++ b/simulation/cpu/pc.vhd
@@ -0,0 +1,34 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity pc is 
+    generic (dsize : integer := 8);
+    port (  trig_clk        : in std_logic;
+            dbus_in_n       : in std_logic;
+            dbus_out_n      : in std_logic;
+            abus_out_n      : in std_logic;
+            int_d_bus       : inout std_logic_vector (dsize - 1 downto 0);
+            int_a_bus       : out std_logic_vector (dsize - 1 downto 0)
+        );
+end pc;
+
+architecture rtl of pc is
+
+signal val : std_logic_vector (dsize - 1 downto 0);
+
+begin
+    int_a_bus <= val when abus_out_n = '0' else
+                (others => 'Z');
+    int_d_bus <= val when (dbus_out_n = '0' and dbus_in_n /= '0') else
+                (others => 'Z');
+
+    set_p : process (trig_clk)
+    begin
+    if ( trig_clk'event and trig_clk = '1') then
+        if (dbus_in_n = '0') then
+            val <= int_d_bus;
+        end if;
+    end if;
+    end process;
+end rtl;
+

diff --git a/simulation/cpu/testbench_cpu_reg.vhd b/simulation/cpu/testbench_cpu_reg.vhd
deleted file mode 100644 (file)
index a3cab6c..0000000
--- a/simulation/cpu/testbench_cpu_reg.vhd
+++ /dev/null
@@ -1,110 +0,0 @@
-
-library IEEE;
-use IEEE.std_logic_1164.all;
---use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
-use std.textio.all;
-
-
-entity testbench_cpu_reg is
-end testbench_cpu_reg;
-
-architecture stimulus of testbench_cpu_reg is 
-    component cpu_reg
-        generic (dsize : integer := 8);
-        port (  clk, en     : in std_logic;
-                d           : in std_logic_vector (dsize - 1 downto 0);
-                q           : out std_logic_vector (dsize - 1 downto 0)
-            );
-    end component;
-    constant interval : time := 15 ns;
-    constant dsize1 : integer := 1;
-    constant dsize8 : integer := 8;
-    constant dsize16 : integer := 16;
-    signal cclk, een : std_logic;
-    signal dd1, qq1    : std_logic_vector (dsize1 - 1 downto 0);
-    signal dd8, qq8    : std_logic_vector (dsize8 - 1 downto 0);
-    signal dd16, qq16    : std_logic_vector (dsize16 - 1 downto 0);
-begin
-    dut0 : cpu_reg generic map (dsize1) port map (cclk, een, dd1, qq1);
-    dut1 : cpu_reg generic map (dsize8) port map (cclk, een, dd8, qq8);
-    dut2 : cpu_reg generic map (dsize16) port map (cclk, een, dd16, qq16);
-
-    p1 : process
-    variable i : integer := 0;
-    constant loopcnt : integer := 10;
-    begin
-
-        for i in 0 to loopcnt * 2 loop
-            cclk <= '1';
-            wait for interval / 2;
-            cclk <= '0';
-            wait for interval / 2;
-        end loop;
-    end process;
-
-    p2 : process
-    variable i : integer := 0;
-    constant loopcnt : integer := 5;
-    begin
-
-        wait for interval / 4;
-
-        for i in 0 to loopcnt loop
-            dd1 <= conv_std_logic_vector(i, dsize1);
-            dd8 <= conv_std_logic_vector(i, dsize8);
-            dd16 <= conv_std_logic_vector(i, dsize16);
-            wait for interval / 4;
-        end loop;
-
-        een <= '1';
-
-        for i in 0 to loopcnt * 3 loop
-            dd1 <= conv_std_logic_vector(i, dsize1);
-            dd8 <= conv_std_logic_vector(i, dsize8);
-            dd16 <= conv_std_logic_vector(i, dsize16);
-            wait for interval / 3;
-        end loop;
-
-        for i in 0 to loopcnt * 4 loop
-            dd1 <= conv_std_logic_vector(i, dsize1);
-            dd8 <= conv_std_logic_vector(i, dsize8);
-            dd16 <= conv_std_logic_vector(i, dsize16);
-            wait for interval / 4;
-        end loop;
-
-        for i in 0 to loopcnt * 5 loop
-            dd1 <= conv_std_logic_vector(i, dsize1);
-            dd8 <= conv_std_logic_vector(i, dsize8);
-            dd16 <= conv_std_logic_vector(i, dsize16);
-            wait for interval / 5;
-        end loop;
-
-        for i in 0 to loopcnt * 2 loop
-            dd1 <= conv_std_logic_vector(i, dsize1);
-            dd8 <= conv_std_logic_vector(i, dsize8);
-            dd16 <= conv_std_logic_vector(i, dsize16);
-            wait for interval;
-        end loop;
-        
-        for i in 0 to loopcnt * 2 loop
-            dd1 <= conv_std_logic_vector(i, dsize1);
-            dd8 <= conv_std_logic_vector(i, dsize8);
-            dd16 <= conv_std_logic_vector(i, dsize16);
-            wait for interval * 2;
-        end loop;
-
-        een <= '0';
-
-        for i in 0 to loopcnt * 3 loop
-            dd1 <= conv_std_logic_vector(i, dsize1);
-            dd8 <= conv_std_logic_vector(i, dsize8);
-            dd16 <= conv_std_logic_vector(i, dsize16);
-            wait for interval / 3;
-        end loop;
-
-        wait;
-    end process;
-
-end stimulus ;
-

diff --git a/simulation/cpu/testbench_pc.vhd b/simulation/cpu/testbench_pc.vhd
new file mode 100644 (file)
index 0000000..b55ddca
--- /dev/null
+++ b/simulation/cpu/testbench_pc.vhd
@@ -0,0 +1,85 @@
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+--use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use std.textio.all;
+
+
+entity testbench_pc is
+end testbench_pc;
+
+architecture stimulus of testbench_pc is 
+    component pc
+        generic (dsize : integer := 8);
+        port (  trig_clk    : in std_logic;
+                dbus_in_n       : in std_logic;
+                dbus_out_n      : in std_logic;
+                abus_out_n      : in std_logic;
+                int_d_bus       : inout std_logic_vector (dsize - 1 downto 0);
+                int_a_bus       : out std_logic_vector (dsize - 1 downto 0)
+            );
+    end component;
+
+    constant interval : time := 15 ns;
+    constant dsize8 : integer := 8;
+    signal cclk: std_logic;
+    signal dbus_in_n: std_logic;
+    signal dbus_out_n: std_logic;
+    signal abus_out_n: std_logic;
+
+    signal id_bus, ia_bus    : std_logic_vector (dsize8 - 1 downto 0);
+
+begin
+    dut1 : pc generic map (dsize8) port map (cclk, dbus_in_n, dbus_out_n, abus_out_n, 
+            id_bus, ia_bus);
+
+    p1 : process
+    begin
+
+        cclk <= '1';
+        wait for interval / 2;
+        cclk <= '0';
+        wait for interval / 2;
+    end process;
+
+    p2 : process
+    variable i : integer := 0;
+    constant loopcnt : integer := 5;
+    begin
+
+        abus_out_n <= '1';
+        dbus_in_n <= '1';
+        dbus_out_n <= '1';
+
+        --set value.
+        id_bus <= conv_std_logic_vector(10, dsize8);
+        wait for interval;
+        dbus_in_n <= '0';
+        wait for interval;
+
+        dbus_in_n <= '1';
+        dbus_out_n <= '0';
+        wait for interval;
+
+        dbus_out_n <= '1';
+        abus_out_n <= '0';
+        wait for interval;
+
+        abus_out_n <= '1';
+        id_bus <= conv_std_logic_vector(100, dsize8);
+        wait for interval;
+        abus_out_n <= '0';
+        wait for interval;
+        abus_out_n <= '1';
+
+        id_bus <= (others => 'Z');
+        dbus_out_n <= '0';
+        wait for interval;
+        dbus_out_n <= '1';
+
+        wait;
+    end process;
+
+end stimulus ;
+