cpu dma set ok.

diff --git a/de0_cv_nes/mos6502.vhd b/de0_cv_nes/mos6502.vhd
index 37b7c88..3d41a3d 100644 (file)
--- a/de0_cv_nes/mos6502.vhd
+++ b/de0_cv_nes/mos6502.vhd
@@ -232,13 +232,15 @@ signal reg_d_in     : std_logic_vector (7 downto 0);
 signal reg_d_out    : std_logic_vector (7 downto 0);\r
 \r
 signal reg_nmi_handled  : integer range 0 to 1;\r
+signal reg_dma_set      : integer range 0 to 1;\r
+\r
 \r
 begin\r
     --state transition process...\r
     set_stat_p : process (pi_rst_n, pi_base_clk)\r
     begin\r
         if (pi_rst_n = '0') then\r
-            reg_main_state <= ST_IDLE;\r
+            reg_main_state <= ST_RS_T0;\r
             reg_sub_state <= ST_SUB00;\r
         elsif (rising_edge(pi_base_clk)) then\r
             reg_main_state <= reg_main_next_state;\r
@@ -324,21 +326,29 @@ begin
     --state change to next.\r
     tx_next_main_stat_p : process (pi_rst_n, reg_main_state, reg_sub_state,\r
                                    reg_inst, reg_tmp_condition, reg_tmp_pg_crossed,\r
-                                   pi_nmi_n, reg_nmi_handled)\r
+                                   pi_nmi_n, reg_nmi_handled, reg_dma_set, pi_rdy)\r
 \r
     begin\r
         case reg_main_state is\r
             -----idle...\r
             when ST_IDLE =>\r
                 if (pi_rst_n = '0') then\r
-                    reg_main_next_state <= reg_main_state;\r
-                else\r
                     reg_main_next_state <= ST_RS_T0;\r
+                elsif (reg_sub_state = ST_SUB73 and reg_dma_set = 1 and pi_rdy = '1') then\r
+                    --ST_CM_T0 is canceled when dma initiated.\r
+                    --redo ST_CM_T0.\r
+                    reg_main_next_state <= ST_CM_T0;\r
+                else\r
+                    reg_main_next_state <= reg_main_state;\r
                 end if;\r
             -----reset...\r
             when ST_RS_T0 =>\r
                 if (reg_sub_state = ST_SUB73) then\r
-                    reg_main_next_state <= ST_RS_T1;\r
+                    if (pi_rst_n = '0') then\r
+                        reg_main_next_state <= reg_main_state;\r
+                    else\r
+                        reg_main_next_state <= ST_RS_T1;\r
+                    end if;\r
                 else\r
                     reg_main_next_state <= reg_main_state;\r
                 end if;\r
@@ -391,6 +401,9 @@ begin
                     if (pi_nmi_n = '0' and reg_nmi_handled = 0) then\r
                         --nmi raised. transit to nmi state.\r
                         reg_main_next_state <= ST_NM_T1;\r
+                    elsif (pi_rdy = '0') then\r
+                        --dma started.\r
+                        reg_main_next_state <= ST_IDLE;\r
                     else\r
                         ---instruction decode next state.\r
                         reg_main_next_state <= inst_decode_rom(conv_integer(reg_inst));\r
@@ -1160,6 +1173,11 @@ end;
                     reg_oe_n    <= '1';\r
                     reg_we_n    <= '1';\r
                     reg_addr    <= (others => 'Z');\r
+                elsif (pi_rdy = '0') then\r
+                    --dma started cycle.\r
+                    reg_oe_n    <= 'Z';\r
+                    reg_we_n    <= 'Z';\r
+                    reg_addr    <= (others => 'Z');\r
                 else\r
                     --normal cycle.\r
                     reg_oe_n    <= '0';\r
@@ -2350,5 +2368,20 @@ end;
             end if;\r
         end if;--if (pi_rst_n = '0') then\r
     end process;\r
+\r
+    --dma flag process...\r
+    dma_set_p : process (pi_rst_n, pi_base_clk)\r
+    begin\r
+        if (pi_rst_n = '0') then\r
+            reg_dma_set <= 0;\r
+        elsif (rising_edge(pi_base_clk)) then\r
+            if (pi_rdy = '0') then\r
+                reg_dma_set <= 1;\r
+            elsif (reg_main_state = ST_CM_T0) then\r
+                reg_dma_set <= 0;\r
+            end if;\r
+        end if;--if (pi_rst_n = '0') then\r
+    end process;\r
+\r
 end rtl;\r
 \r